Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications

Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications

“…3(b) the F-1T1R normalized current variation ∆I/I L vs I L . A large ∆I corresponds to a larger signal on the summation line, which relaxes the ADC specifications [2]. From the simulations, ∆I/I L is maximized in W.I.…”

“…The scheme in Fig. 2(a) includes a digital-to-time D/A converter (DAC) to drive the gates of the MOS switches of the 1T1R cells, on the same row, with the pulse-width modulated (PWM) signal V DD • act i (t) 1 [2]. The length of the pulse is proportional to the activation value, i.e., T M AC • a i with a i ∈ [0, 1].…”

“…In recent years, mixed-signal accelerators have emerged as a valuable solution to maximize throughput and energy efficiency, in DNN algorithm execution. These processing units operate with low precision operands, obtaining high classification accuracy, with a great reduction of energy consumption [2]. Accelerators exploit the concept of Analog in-Memory Computation (AiMC) to reduce data movement between memory and processor [3].…”

“…By the inclusion of these memories, mixed-signal accelerators can outperform the standard SRAM-based implementations, at the cost of additional challenges in process integration and circuit A. Boni, F. Malena, F. Saccani, M. Amoretti, and M. Caselli are with the Department of Engineering and Architecture, University of Parma, 43124 Parma, Italy (e-mail: andrea.boni@unipr.it). design [2]. Among non-standard devices, Resistive Random Access Memory (RRAM) are non-volatile, with potential high memory density, and can offer multi-bit weight capability [4].…”

“…The low value of the programmable resistance is particularly critical for the computation linearity, making the MVM result severely affected by the IR drop along the column. This forces countermeasures in hardware, including integrator circuit or transimpedance amplifier (TIA) to clamp SL, with penalties for accelerator area and energy consumption [2]. Reducing the number of cells in computation can also alleviate this issue, but it also reduces the energy efficiency [7].…”