Memory Management Techniques for Exploiting RDMA in PGAS Languages

Dalton, Barnaby; Tanase, Gabriel; Alvanos, Michail; Almasi, Gheorghe; Tiotto, Ettore

doi:10.1007/978-3-319-17473-0_13

Cited by 2 publications

(3 citation statements)

References 19 publications

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“…Before accessing shared pointers, the compiler also creates calls to shared pointer arithmetic ( ptr arithmetic). The shared pointer is a fat pointer that contains information about the offset and the thread [7]. …”

Section: Unified Parallel Cmentioning

confidence: 99%

Using shared-data localization to reduce the cost of inspector-execution in unified-parallel-C programs

et al. 2016

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Programs written in the Unified Parallel C (UPC) language can access any location of the entire local and remote address space via read/write operations. However, UPC programs that contain fine-grained shared accesses can exhibit performance degradation. One solution is to use the inspector-executor technique to coalesce fine-grained shared accesses to larger remote access operations. A straightforward implementation of the inspectorexecutor transformation resultin excessive instrumentation that hinders performance.This paper addresses this issue and introduces various techniques that aim at reducing the generated instrumentation code: a shared-data localization transformation based on Constant-Stride Linear Memory Descriptors (CSLMADs) [32], the inlining of data locality checks and the usage of an index vector to aggregate the data. Finally, the paper introduces a lightweight * Corresponding author loop code motion transformation to privatize shared scalars that were propagated through the loop body. A performance evaluation, using up to 2048 cores of a POWER 775, explores the impact of each optimization and characterizes the overheads of UPC programs. It also shows that the presented optimizations increase performance of UPC programs up to 1.8× their UPC hand-optimized counterpart for applications with regular accesses and up to 6.3× for applications with irregular accesses.

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Section: Unified Parallel Cmentioning

confidence: 99%

Using shared-data localization to reduce the cost of inspector-execution in unified-parallel-C programs

et al. 2016

Self Cite

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“…Although this provides good results for applications exhibiting regular memory access patterns, it still has a performance overhead due to the inspector/executor loop and scheduling, which in some cases can reduce the performance by an order of magnitude compared to hand-optimized code. In Dalton et al [2014], symmetric heap mirroring is presented to reduce the performance cost of threads accessing elements in a shared memory space. Although reduced, the authors note that a substantive overhead still remains.…”

Section: Related Workmentioning

confidence: 99%

“…At least two different implementations are possible for the address translation: (1) the base address can be computed directly from the thread number (similarly to Fröning and Litz [2010] and Dalton et al [2014]) because the thread address spaces start at regular intervals, or (2) a lookup table can be used to retrieve the base address. The first method is more restrictive in terms of the possible addresses used but is more scalable, as it does not require storing a complete base addresses table.…”

Section: Pgas Memory Model Hardware Supportmentioning

confidence: 99%

Enabling PGAS Productivity with Hardware Support for Shared Address Mapping

Serres

Kayi

Anbar

et al. 2015

ACM Trans. Archit. Code Optim.

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Due to its rich memory model, the partitioned global address space (PGAS) parallel programming model strikes a balance between locality-awareness and the ease of use of the global address space model. Although locality-awareness can lead to high performance, supporting the PGAS memory model is associated with penalties that can hinder PGAS's potential for scalability and speed of execution. This is because mapping the PGAS memory model to the underlying system requires a mapping process that is done in software, thereby introducing substantial overhead for shared accesses even when they are local. Compiler optimizations have not been sufficient to offset this overhead. On the other hand, manual code optimizations can help, but this eliminates the productivity edge of PGAS. This article proposes a processor microarchitecture extension that can perform such address mapping in hardware with nearly no performance overhead. These extensions are then availed to compilers through extensions to the processor instructions. Thus, the need for manual optimizations is eliminated and the productivity of PGAS languages is unleashed. Using Unified Parallel C (UPC), a PGAS language, we present a case study of a prototype compiler and architecture support. Two different implementations of the system were realized. The first uses a full-system simulator, gem5, which evaluates the overall performance gain of the new hardware support. The second uses an FPGA Leon3 soft-core processor to verify implementation feasibility and to parameterize the cost of the new hardware. The new instructions show promising results on all tested codes, including the NAS Parallel Benchmark kernels in UPC. Performance improvements of up to 5.5× for unmodified codes, sometimes surpassing handoptimized performance, were demonstrated. We also show that our four-core FPGA prototype requires less than 2.4% of the overall chip's area.

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Memory Management Techniques for Exploiting RDMA in PGAS Languages

Cited by 2 publications

References 19 publications

Using shared-data localization to reduce the cost of inspector-execution in unified-parallel-C programs

Using shared-data localization to reduce the cost of inspector-execution in unified-parallel-C programs

Enabling PGAS Productivity with Hardware Support for Shared Address Mapping

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