Memory reduced MAP decoding for double-binary turbo decoder

Abstract

Abstract:In this paper, we proposed the branch metric recovery scheme to reduce the memory requirement of MAP decoding for doublebinary convolutional turbo code. The proposed technique exploits the fact that huge memory size is required to store the branch metrics in double-binary convolutional turbo decoder. In the proposed method, rather than storing the original branch metrics, the partial terms of the branch metric are stored and the branch metrics are recovered with simple additions. The implementation results based on the proposed technique are presented to show the extremely low overhead compared to the huge memory reduction. Keywords: MAP decoding, max-log-MAP, double-binary turbo code Classification: Wireless communication hardware References

High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

“…However, even though the SISO decoding architecture uses sliding window technique, the SISO decoder which consists of Type-C2 or Type-L2 requires huge memory resources to store path metrics and branch metrics. To reduce the branch metric memory requirement, previous work [16] can be exploited. This paper proposes the memory reduction technique for forward memory in MAP(maximum a posteriori)-based radix-4 SISO algorithm for turbo decoder.…”

“…9, the sliding window technique, where a large frame is split into a number of small windows and the decoding algorithm is applied to each window independently, is used for reducing the memory size required to store path metrics [16]. The forward metrics are calculated prior to backward metrics and these will be stored on forward memory.…”

“…(15) (16) Even though the cost of hardware overhead incurred by recovery circuit is increased in terms of one MUX and one register, the critical path of Type-C3 and Type-L3 is maintained to have same delay with that of Type-C2 and Type-L2, respectively. The requirement of forward memory which stores original path metric instead of recursive metrics is hugely reduced by more than 75% compared to previous retimed radix-4 SISO decoder architectures without recovery circuit.…”

“…In addition, since all path metrics are normalized by subtracting the P NORM which is same with one of the eight path metrics at the same state for avoiding overflow, one path metric among the eight path metrics does not need to be stored. The number of metrics to be stored can be reduced from 8 to 7 [16].…”