Memory Reduction Techniques for Logarithmic Number System

Balaji, G.B.; Balaji, K.; Sundararaman, Harissh; Naveen, A.; Santha, K.R.

doi:10.1109/icscn.2007.350772

Cited by 1 publication

(1 citation statement)

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“…The speed was limited mainly by the delay in multipliers and adders. An effective solution is to exploit the unique feature of the Logarithmic Number System (LNS), which can convert multiplications into additions [6]. In such a solution, it would be critical to have an efficient implementation of an adder and the conversion between the conventional number system (CNS) and the Logarithmic Number System (LNS).…”

Section: Introductionmentioning

confidence: 99%

A High-Performance 8-Tap FIR Filter Using Logarithmic Number System

Sun

Kim

2011

2011 IEEE International Conference on Communications (ICC)

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This paper presents an approach to implement a high-performance 8-tap digital FIR (Finite Impulse Response) filter using the Logarithmic Number System. In the past, FIR filters were implemented by a conventional number system; their speed was limited because of the multiply-accumulate operations. We realize a fast FIR filter by utilizing the Logarithmic Number System, which allows a simple implementation of multiplication using a fixed-point adder. And the serious demerit of Logarithmic Number System's algorithm, conversions to and from the conventional number representations, is effectively overcome by pipelining to reduce the delay and complexity of the filter. The critical path was reduced from a multiply-accumulate operation to an add operation. Our FIR filter can operate at 1.3 GHz under the condition of 1.2 V power supply using the SMIC 0.13 µm CMOS technology, and requires 27% less area than the original FIR filter.

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Section: Introductionmentioning

confidence: 99%