Memory Requirement Reduction of Deep Neural Networks for Field Programmable Gate Arrays Using Low-Bit Quantization of Parameters

Nicodemo, Niccolò; Naithani, Gaurav; Drossos, Konstantinos; Virtanen, Tuomas; Saletti, Roberto

doi:10.23919/eusipco47968.2020.9287739

Cited by 4 publications

(2 citation statements)

References 13 publications

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“…The reduction in the size of the speech separation model was considered in [ 76 ]. The authors proposed a low-bit quantization method based on nonuniform and dynamic quantization methods (where the parameters of the quantization are adjusted according to the data).…”

Section: Techniques For the Reduction In Computational And Memory Req...mentioning

confidence: 99%

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A Survey on Low-Latency DNN-Based Speech Enhancement

Drgas

2023

Sensors

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This paper presents recent advances in low-latency, single-channel, deep neural network-based speech enhancement systems. The sources of latency and their acceptable values in different applications are described. This is followed by an analysis of the constraints imposed on neural network architectures. Specifically, the causal units used in deep neural networks are presented and discussed in the context of their properties, such as the number of parameters, the receptive field, and computational complexity. This is followed by a discussion of techniques used to reduce the computational complexity and memory requirements of the neural networks used in this task. Finally, the techniques used by the winners of the latest speech enhancement challenges (DNS, Clarity) are shown and compared.

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Section: Techniques For the Reduction In Computational And Memory Req...mentioning

confidence: 99%

“…Quantization can also lead to a reduction in model size of more than 50%. In some cases (for example, [ 76 ]), this at the cost of a small reduction in STOI (by 2.7%). It is also possibly to speed up the quantization when integer computations are appropriately used.…”

Section: Techniques For the Reduction In Computational And Memory Req...mentioning

confidence: 99%

A Survey on Low-Latency DNN-Based Speech Enhancement

Drgas

2023

Sensors

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Performance/Resources Comparison of Hardware Implementations on Fully Connected Network Inference

Lozada

Ruiz²,

Rodríguez³

et al. 2022

Intelligent Data Engineering and Automated Learning – IDEAL 2022

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Resource-constrained FPGA/DNN co-design

Zhang

Kouzani

2021

Neural Comput & Applic

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Deep neural networks (DNNs) have demonstrated super performance in most learning tasks. However, a DNN typically contains a large number of parameters and operations, requiring a high-end processing platform for high-speed execution. To address this challenge, hardware-and-software co-design strategies, which involve joint DNN optimization and hardware implementation, can be applied. These strategies reduce the parameters and operations of the DNN, and fit it into a low-resource processing platform. In this paper, a DNN model is used for the analysis of the data captured using an electrochemical method to determine the concentration of a neurotransmitter and the recoding electrode. Next, a DNN miniaturization algorithm is introduced, involving combined pruning and compression, to reduce the DNN resource utilization. Here, the DNN is transformed to have sparse parameters by pruning a percentage of its weights. The Lempel-Ziv-Welch algorithm is then applied to compress the sparse DNN. Next, a DNN overlay is developed, combining the decompression of the DNN parameters and DNN inference, to allow the execution of the DNN on a FPGA on the PYNQ-Z2 board. This approach helps avoid the need for inclusion of a complex quantization algorithm. It compresses the DNN by a factor of 6.18, leading to about 50% reduction in the resource utilization on the FPGA. Keywords Lempel-Ziv-Welch compression Á Deep neural network Á Hardware-and-software co-design Á Electrochemical sensing Á Field-programmable gate array Neural Computing and Applications

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Memory Requirement Reduction of Deep Neural Networks for Field Programmable Gate Arrays Using Low-Bit Quantization of Parameters

Cited by 4 publications

References 13 publications

A Survey on Low-Latency DNN-Based Speech Enhancement

A Survey on Low-Latency DNN-Based Speech Enhancement

Performance/Resources Comparison of Hardware Implementations on Fully Connected Network Inference

Resource-constrained FPGA/DNN co-design

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