Memory Safety for Embedded Devices with nesCheck

Midi, Daniele; Payer, Mathias; Bertino, Elisa

doi:10.1145/3052973.3053014

Cited by 25 publications

(10 citation statements)

References 29 publications

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“…With the rapid increase in popularity of Internet-of-Things devices, one may be wary of the compromises made in terms of security in order to achieve increased compatibility and power efficiency. It is our hope 2 Common Vulnerabilities and Exposures: https://cve.mitre.org/cve that this analysis can be a first step in evaluating the control-flow integrity of such embedded operating systems.…”

Section: Discussionmentioning

confidence: 99%

“…2 However, there were challenges in obtaining old variants of such software for each operating system that we chose to investigate. For compatibility reasons and so that the comparisons being made are with the same software, we decided to develop our own vulnerable software.…”

Section: Limitationsmentioning

confidence: 99%

“…Buffer-overflow attacks are one of the most common classes of exploits against the control-flow integrity of computer systems. With increased reliance on embedded cyber-physical systems and software-defined networking, buffer-overflow attacks can damage much more than the individual system exploited [1], [2]. This threat is further complicated by the general reliance of organizations on third-party and closed-source software.…”

Section: Introductionmentioning

confidence: 99%

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ASLR: How Robust Is the Randomness?

Ganz

Peisert

2017

2017 IEEE Cybersecurity Development (SecDev)

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Abstract-This paper examines the security provided by different implementations of Address Space Layout Randomization (ASLR). ASLR is a security mechanism that increases control-flow integrity by making it more difficult for an attacker to properly execute a buffer-overflow attack, even in systems with vulnerable software. The strength of ASLR lies in the randomness of the offsets it produces in memory layouts. We compare multiple operating systems, each compiled for two different hardware architectures, and measure the amount of entropy provided to a vulnerable application. Our paper is the first publication that we are aware of that quantitatively compares the entropy of different ASLR implementations. In addition, we provide a method for remotely assessing the efficacy of a particular security feature on systems that are otherwise unavailable for analysis, and highlight the need for independent evaluation of security mechanisms.

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Section: Discussionmentioning

confidence: 99%

Section: Limitationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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ASLR: How Robust Is the Randomness?

Ganz

Peisert

2017

2017 IEEE Cybersecurity Development (SecDev)

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“…Research projects also tackle the memory protection problem on a programming-language level for embedded devices. nesCheck [14] modifies the language and compiler to perform stronger type safety, static analysis, and run-time checks. Others develop new compiler frameworks to address stack, array and pointer safety, and implement new heap allocation techniques [15].…”

Section: A State-of-the-artmentioning

confidence: 99%

“…Existing embedded system memory protections mediate access only to large segments of code and data. Protecting finer granularities often requires explicit checks from the compiler or programmer at a cost of run-time slowdown [15] [14], and can be error-prone or incomplete [2]. An architecture should provide a generic mechanism for low-cost and fine-grained memory protection.…”

Section: Requirementsmentioning

confidence: 99%

CheriRTOS: A Capability Model for Embedded Devices

Xia

Woodruff

Barral

et al. 2018

2018 IEEE 36th International Conference on Computer Design (ICCD)

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Embedded systems are deployed ubiquitously among various sectors including automotive, medical, robotics and avionics. As these devices become increasingly connected, the attack surface also increases tremendously; new mechanisms must be deployed to defend against more sophisticated attacks while not violating resource constraints. In this paper we present CheriRTOS on CHERI-64, a hardware-software platform atop Capability Hardware Enhanced RISC Instructions (CHERI) for embedded systems. Our system provides efficient and scalable task isolation, fast and secure inter-task communication, fine-grained memory safety, and real-time guarantees, using hardware capabilities as the sole protection mechanism. We summarize state-of-the-art security and memory safety for embedded systems for comparison with our platform, illustrating the superior substrate provided by CHERI's capabilities. Finally, our evaluations show that a capability system can be implemented within the constraints of embedded systems.

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Security for Software on Tiny Devices

Bagchi

2022

Springer Series in Reliability Engineering

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Memory Safety for Embedded Devices with nesCheck

Cited by 25 publications

References 29 publications

ASLR: How Robust Is the Randomness?

ASLR: How Robust Is the Randomness?

CheriRTOS: A Capability Model for Embedded Devices

Security for Software on Tiny Devices

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