Memristive device based on a depletion-type SONOS field effect transistor

Abstract

State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON /R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

Self‐Powered Artificial Mechanoreceptor Based on Triboelectrification for a Neuromorphic Tactile System

“…By controlling the electron trap density in the charge trap layer of silicon nitride (Si 3 N 4 ), the threshold voltage ( V T ) and the conductance can be modulated to determine the synaptic weight, as shown in Figure S7c,d , Supporting Information. [ 43 , 44 ] At a fixed drain voltage of V DD = 1 V, the output current from the SONOS‐synapse ( I syn ) was measured with a parameter analyzer. Although we used a parameter analyzer for this measurement, the measurement units can be commonly embedded in a chip of a mobile phone for mobile healthcare applications, as conceptually illustrated in Figure 6a .…”

A Recoverable Synapse Device Using a Three‐Dimensional Silicon Transistor

“…The fabrication process is explained in detail in Figure S1 in the Supporting Information. The two n + ‐doped S/D components act as respective postsynaptic and presynaptic neuron terminals, while the postsynaptic n + ‐doped S is connected to the poly‐Si gate, forming a two‐terminal synapse device . With a positive presynaptic pulse, electrons flow out from the Si 3 N 4 layer, which results in a highly conductive channel due to detrapping, analogous to synaptic potentiation.…”

Sub-1 nm Equivalent Oxide Thickness Al-HfO2 Trapping Layer with Excellent Thermal Stability and Retention for Nonvolatile Memory

“…8 In particular, CT memories are also interesting as memristors in on-chip solutions for neural networks and neuromorphic computing. 9,10 Finally, CT stacks are also a simple and viable technology for memory devices exploiting new/alternative channel materials (e.g., two-dimensional crystals) 11 and/or toward Flash memory cells on transparent substrates. 12 In this framework, the promising performance already achieved by the CT cells (even in planar technology) may be further improved by the introduction in the memory stack of new performing materials, such as high-k oxides and nanolaminates as charge trapping layer.…”

“…Furthermore, CT technology is typically characterized by a much simpler process flow and a higher compatibility with standard CMOS compared to FG technology and, therefore, it is also very promising for embedded memories and system-on-chip products . In particular, CT memories are also interesting as memristors in on-chip solutions for neural networks and neuromorphic computing. , Finally, CT stacks are also a simple and viable technology for memory devices exploiting new/alternative channel materials (e.g., two-dimensional crystals) and/or toward Flash memory cells on transparent substrates …”