Memristive Power Optimization of Non-volatile Seven Transistors Static Random Access Memory Cell

Abstract

Starting from the consecutive properties of Memristor, researchers identify that using a non-linear element "Memristor" into the circuit, the power consumption of the design will be reduced to a great extent. Memristor acts as a conventional resistor, but it has a memory which stores data in the form of resistance. A new Seven Transistors (7T) based Static Random Access Memory (SRAM) cell using memristors is designed in this manuscript that provides low power as well as non-volatile functionality to the cell. Such hybrid CMOSMemristor's combination gives robustness, consistency and higher functionality to the CMOS subsystem. With the proposed 7T SRAM circuit, we observed that the Average Power (0.234 µW), Total Power (10.08 µW), Static Power (20.83 pW) and Dynamic Power (0.01 µW) are reduced over the conventional 7T SRAM circuits. Different low-power optimization tools and device modeling were discovered to make more accurate power consumption calculations. There will be a need of designing such devices which are essential for the VLSI circuit designers. Memristor verifies itself to be a strong contender for the growing demands of Low power and Portable applications. Simulation of the SRAM design has been done in a 45 nm CMOS environment with the help of Cadence Virtuoso tool, and the recorded results depicted the advantages of proposed design over the CMOS based SRAM cell.

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

“…In fact, this feature of power‐gating and also the idea of employing output inverter in read path, lead to have a stable bitcell with small powers, compared to other works (Tables 1–3). Other works often reduced delays at the cost of higher power‐consumptions [10–75].…”

“…Also, it has an acceptable leakage current and static/dynamic powers (Table 3). Note that other works were not designed for operating at threshold supply‐voltage ($${V}_{\text{DD}}$$ = $${V}_{\text{th}}$$), as well as, they just reduced their delays at the cost of higher power‐consumptions [10–75] which are not suitable for implementing in chipset of portable devices. As a result, this 11T bitcell (Figure 9) can be considered as a final optimum design that this paper tries to reach it from the beginning.…”

“…In recent decades, many efforts have been made by researchers to offer optimum designs for bitcell. They declared that thanks to the CNTs, CNTFETs have been considered as a promising alternative for Complementary Metal Oxide Semiconductors (CMOSs) in low power SRAMs [10–75], however, CNFET fabrication process still has some imperfections, including the presence of metallic carbon nanotubes ( m ‐CNTs), imperfect m ‐CNT removal processes, chirality drift, CNT doping variations, and density fluctuations, etc. [76–79].…”