Memristive Stateful Logic for Edge Boolean Computers

Kim, Young Seok; Son, Myeong Won; Kim, Kyung Min

doi:10.1002/aisy.202000278

Cited by 27 publications

(21 citation statements)

References 101 publications

(196 reference statements)

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“…So far, many types of IMC logic gates have been proposed and compared in terms of latency and area, [10,26,[55][56][57] but the reliability of logic operations has not been fully considered. Reliability is still an open challenge for memristive IMC logic gates, and there is actively ongoing research to address related issues such as state drift and soft error.…”

Section: κ Mapping Analysis Methods Using the Calculation Of Device S...mentioning

confidence: 99%

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Park

Kim

et al. 2022

Advanced Intelligent Systems

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The development of memristor‐based stateful logic circuits can minimize data movement during the computing process to achieve in‐memory computing, mitigating the von Neumann bottleneck in the current computing architecture. Herein, a method to combine resistance–resistance (R–R) and voltage–resistance (V–R) logic gates to implement exclusive logic gates composed of APMR‐two‐2(XOR, IMP, RIMP) and APMR‐three‐4XOR, where APMR means antiparallel memristors with a series resistor, is suggested. The proposed gates can accelerate XOR logic operation in a single cycle and expand for the n‐bit input. The performance of the proposed logic gate is then demonstrated with a 1‐bit full adder–subtractor along with the comparison of an n‐bit ripple carry adder. It shows that the implementation for the n‐bit adder takes 4n+1 memristors within 2n+1 steps, which significantly improves the optimization in terms of space‐ and time‐related costs compared with other memristive logic gates. Subsequently, the improved adder circuit can be further utilized to implement an n‐bit multiplier. In addition, the evaluation of the device stress on the various logic gates confirms that the proposed logic gates are reliable.

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Section: κ Mapping Analysis Methods Using the Calculation Of Device S...mentioning

confidence: 99%

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Park

Kim

et al. 2022

Advanced Intelligent Systems

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show abstract

“…To increase the computational parallelism, the data manipulation of the N-bit adder on the memristor array relies on the bitwise parallelism and blockwise parallelism. [34][35][36][37][38] For bitwise parallel computing, the operands must be aligned before the operation, making the data manipulation more important. As can be inferred from the previous section, each line corresponds to a 1-bit adder, so the N-bit adder needs an n-line parallel operation.…”

Section: A Feasible Circuit Architecture For N-bit Addermentioning

confidence: 99%

Reconfigurable and Efficient Implementation of 16 Boolean Logics and Full‐Adder Functions with Memristor Crossbar for Beyond von Neumann In‐Memory Computing

Song

Wang

et al. 2022

Advanced Science

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The rise of emerging technologies such as Big Data, the Internet of Things, and artificial intelligence, which requires efficient power schemes, is driving brainstorming in data computing and storage technologies. In this study, merely relying on the fundamental structure of two memristors and a resistor, arbitrary Boolean logic can be reconfigured and calculated in two steps, while no additional voltage sources are needed beyond "±V P " and 0, and all state reversals are based on memristor set switching. Utilizing the proposed logic scheme in an elegant form of unity structure and minimum cost, the implementation of a 1-bit adder is demonstrated economically, and a promising circuit scheme for the N-bit adder is exhibited. Some critical issues including the crosstalk problem, energy consumption, and peripheral circuits are further simulated and discussed. Compared with existing works on memristive logic, such methods support building a memristor-based digital in-memory calculation system with high functional reconfigurability, simple voltage sources, and low power and area consumption.

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“…2 Implementation of RNIMP gate in [9] based on improved IMP circuit when combining 1T1R arrays state. Logic gates are named using method in [10], and their names are subscripts of their driving voltages.…”

Section: Design Of Threshold Logicmentioning

confidence: 99%

Efficient threshold logic in 1T1R array

Wang

et al. 2022

Electronics Letters

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In-memory computing based on memristor logic is one of the most promising approaches to break the 'memory wall' and 'power wall'. However, some important logics (such as AND and MAJ) cannot be implemented efficiently in 1T1R arrays, which makes it difficult to design low-delay memristor-based logic computing systems. An efficient threshold logic is proposed by adding an auxiliary memristor in MAGIC (N+1)-OR gate and optimising the driving voltage. The proposed threshold logic can be completely implemented in a 1T1R array without any additional resistor, and can achieve AND logic and MAJ logic directly. Furthermore, a 1-bit full adder based on the proposed threshold logic, which only requires three steps and six memristors, is designed. Our proposed threshold logic and full adder design perform advantages in terms of area and delay compared with the previous designs.

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Memristive Stateful Logic for Edge Boolean Computers

Cited by 27 publications

References 101 publications

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Reconfigurable and Efficient Implementation of 16 Boolean Logics and Full‐Adder Functions with Memristor Crossbar for Beyond von Neumann In‐Memory Computing

Efficient threshold logic in 1T1R array

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