SUMMARYEmerging wide-band communications and spectrum-sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far-field beam width. Realizing existing phased-array technology on a digital scale is computationally intensive. Moreover, digitizing wide-band signals at Nyquist rate requires complex high-speed analog-to-digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low-complexity alternative proposed in this paper is the use of radio-frequency (RF) channelizers for spectrum division followed by sub-sampling of the RF sub-bands, which results in extensive reduction of the necessary ADC operative frequency. The RF-channelized array signals are directionally filtered using 2-D digital filterbanks. This mixed-domain RF/digital aperture array allows sub-sampling, without utilizing multi-rate 2-D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14-19 dB of rejection of wide-band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single-phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65-nm Xilinx field-programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area-time complexity, and dynamic power consumption for a 45-nm CMOS circuit operating at B DC = 1.1 V, are presented.