MEMS variable-capacitor phase shifters part I: Loaded-line phase shifter

Zhang, Huantong; Laws, Alexander; Gupta, K.C.; Lee, Y. C.; Bright, Victor M.

doi:10.1002/mmce.10089

Cited by 28 publications

(8 citation statements)

References 22 publications

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“…Over the frequency range 26 -27 GHz, return loss values are better than 13 dB. The minimum seen in the return loss curve is caused by the fact that the hybrid, /4 transformers, and phase shifting circuit have been designed at a single design 1 frequency. This good agreement between measured (179.30°) and design (180°) values of the phase shifters validates the phase-shifter design procedure developed in this article.…”

Section: Characterization Of 180°r Eflection-type Phase Shiftermentioning

confidence: 99%

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MEMS variable-capacitor phase shifters part II: Reflection-type phase shifters

Zhang

Laws

Gupta

et al. 2003

Int J RF and Microwave Comp Aid Eng

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A novel design procedure for reflection-type phase shifters using capacitive devices is developed. Using this approach, a phase shifter for operation at 26.5 GHz is developed using MEMS variable capacitors reported in Part I of this article. A design optimization procedure is discussed. Design of a CPW hybrid at 26.5 GHz (as needed for this phase shifter) is also discussed. Experimental results validate the design procedure and yield a phase shift of 179.30°at 26.5 GHz.

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Section: Characterization Of 180°r Eflection-type Phase Shiftermentioning

confidence: 99%

“…The design and characterization of MEMS variable capacitors and loaded-line phase shifters has been reported in Part I of this article [1]. In this part, we developed a novel design procedure for reflectiontype phase shifters using capacitive devices.…”

Section: Introductionmentioning

confidence: 99%

MEMS variable-capacitor phase shifters part II: Reflection-type phase shifters

Zhang

Laws

Gupta

et al. 2003

Int J RF and Microwave Comp Aid Eng

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“…Since it is generally easier to adjust a constant-frequency (narrow-bandwidth) clock signal, rather than the wide-bandwidth data signal, the solution usually involves adjusting the clock phase. Many VCO and PLL or DLL techniques are widely used for this purpose [1][2][3][4][5][6][7][8].…”

Section: Introduction Background Motivationmentioning

confidence: 99%

Variable delay of multi-gigahertz digital signals for deskew and jitter-injection test applications

Keezer

Minier

Ducharme

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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The ability to precisely control the timing of digital signals is especially important for multi-GHz testing applications where errors are measured in picoseconds or even 100fs. While many solutions exist for continuous clock-type signals, delay of wide-bandwidth data signals is not so easy. In this paper we introduce a novel technique for adjusting the delay of ~7Gbps data signals on a picosecond scale without significant distortion. The approach is based on a timing/amplitude dependency effect observed in a variable-gain SiGe buffer. A prototype is demonstrated with a variable delay range of about 50ps. This circuit is enhanced by adding a "coarse" delay section, including four 33ps steps, to provide the desired total range of ~140ps. The end application requires several of these circuits for deskewing parallel buses of 6.4Gbps ATE signals. The circuit is also useful for injecting a variable amount of jitter, limited by the fine-delay adjustment range.

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“…In the area of micro-actuators, several micro-structures [4,5] have been used as the primitive components. These actuators could be utilized in many applications where the application of a force (picoNewtons), in conjunction with their positioning, is needed [6][7][8].…”

Section: Introductionmentioning

confidence: 99%