Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory system

Minimizing MLC PCM write energy for free through profiling-based state remapping

“…Jiang et al [7] propose to remove possible states so that lower reset currents can be applied to save power. Joshi et al [8] propose to flexibly switch between the "set-followed-by-resets" and the "reset-followed-by-sets" programming strategies according to the objective states. Their technique is only applicable if the target PCM supports both programming strategies in a fine-grained manner.…”

“…MLC PCM PROGRAMMING AND MODELING Resistance levels, which represent different states, are fundamentally determined by the relative amorphous fraction in PCM cells, which is in turn determined by the amount of energy delivered to the GST material during programming. As a result, to achieve different resistance levels, various number of reset/set iterations are needed to precisely deliver appropriate amount of energy [8], [13].…”

Architectural support for designing dependable non-volatile main memories

“…Our main memory is designed using SLC-based PCM 1 . The parameters for the PCM are set to model a standard PCM-based DIMM, similar to to values used in prior work [43,44]. We use the PARSEC benchmark suite [11], providing us with a robust set of multi-threaded workloads.…”

“…The read verification [6,43] is also a part of the PCM technology standard, embedded into the logic of PCM chips. The extra read ensures that the resistance of each cell is within a safe region and is used for error detection as well.…”

“…Multiple resistance ranges in MLC PCMs are used to realize multiple states. Write operations in MLCs are performed using iterative programming and are verified using subsequent read verification [6,43], which ensures that the resistance of each cell is within a safe region. The verification pulses are automatically injected into a closed-loop circuit within a PCM chip, which further exacerbates the wear-out problem [6].…”