Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors

Mohan, Sibin; Mueller, Frank

doi:10.1109/rtss.2008.12

Cited by 10 publications

(6 citation statements)

References 15 publications

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“…Research in static timing analysis for complex core architectures is very active. For example, analyses that derive patterns of cache misses for split level 1 data and instruction caches have been proposed in [14], [22], while the work in [13] derives tight execution bounds by analyzing the pipeline status.…”

Section: System Modelmentioning

confidence: 99%

A Predictable Execution Model for COTS-Based Embedded Systems

Pellizzoni

Betti

Bak

et al. 2011

2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium

206

197

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Abstract-Building safety-critical real-time systems out of inexpensive, non-real-time, COTS components is challenging. Although COTS components generally offer high performance, they can occasionally incur significant timing delays. To prevent this, we propose controlling the operating point of each shared resource (like the cache, memory, and interconnection buses) to maintain it below its saturation limit. This is necessary because the low-level arbiters of these shared resources are not typically designed to provide real-time guarantees. In this work, we introduce a novel system execution model, the PRedictable Execution Model (PREM), which, in contrast to the standard COTS execution model, coschedules at a high level all active components in the system, such as CPU cores and I/O peripherals. In order to permit predictable, system-wide execution, we argue that realtime embedded applications should be compiled according to a new set of rules dictated by PREM. To experimentally validate our theory, we developed a COTS-based PREM testbed and modified the LLVM Compiler Infrastructure to produce PREMcompatible executables.

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Section: System Modelmentioning

confidence: 99%

A Predictable Execution Model for COTS-Based Embedded Systems

Pellizzoni

Betti

Bak

et al. 2011

2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium

206

197

View full text Add to dashboard Cite

show abstract

“…Timing analysis determines an application's BCET and WCET bound that allows verification if a task's deadline can always be met. Timing analysis can be performed via dynamic [3], [25], static techniques [27], [15] or hybrids of them [2], [14], [26]. Dynamic timing analysis determines the effect of different inputs on execution time to approximate the WCET, e.g., to determine that an inversely sorted list maximizes bubblesort's computational complexity.…”

Section: Attack Model and Scenariomentioning

confidence: 99%

Time-based intrusion detection in cyber-physical systems

Zimmer

Bhat

Mueller

et al. 2010

Proceedings of the 1st ACM/IEEE International Conference on Cyber-Physical Systems

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Abstract-Embedded systems, particularly real-time systems with temporal constraints, are increasingly deployed in every day life. Such systems that interact with the physical world are also referred to as cyber-physical systems (CPS). These systems commonly find use in critical infrastructure from transportation to health care. While security in CPS-based real-time embedded systems has been an afterthought, it is becoming a critical issue as these systems are increasingly networked and inter-dependent. The advancement in their functionality has resulted in more conspicuous interfaces that may be exploited to attack them.In this paper, we present three mechanisms for time-based intrusion detection. More specifically, we detect the execution of unauthorized instructions in real-time CPS environments. Such intrusion detection utilizes information obtained by static timing analysis. For real-time CPS systems, timing bounds on code sections are readily available as they are already determined prior to the schedulability analysis. We demonstrate how to provide micro-timings for multiple granularity levels of application code. Through bounds checking of these micro-timings, we develop techniques to detect intrusions (1) in a self-checking manner by the application and (2) through the operating system scheduler, which are novel contributions to the real-time/embedded systems domain to the best of our knowledge.

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“…WCET analysis of the program must take the WCETs of these instructions into account: a time-predictable architecture attempts to ensure that this is possible [1,20]. Time-predictable architecture research may focus on the instruction memory subsystem [15], the CPU [13], or the data memory subsystem [8,21]. SMMU research is in the latter category [24].…”

Section: Time-predictable Data Memorymentioning

confidence: 99%

Investigating Average versus Worst-Case Timing Behavior of Data Caches and Data Scratchpads

Whitham

Audsley

2010

2010 22nd Euromicro Conference on Real-Time Systems

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This paper shows that a program using a timepredictable memory system for data storage can achieve a similar worst-case execution time (WCET) to the average-case execution time (ACET) using a conventional heuristic-based memory system including a data cache. This result is useful within any embedded system where time-predictability and performance are both important, particularly hard real-time systems carrying out intensive data processing activities. It is a counter-example to the conventional wisdom that time-predictable means "slow" in comparison to ACET-focused heuristics.To carry out the investigation, 36 "memory access models" are derived from benchmark programs and assumed to be representative of typical code. The models generate LOAD/STORE instructions to exercise a data cache or scratchpad memory management unit (SMMU). The ACET is determined for the data cache and the WCET is determined for the SMMU. After improvements are applied, results show that the SMMU WCET is within 5% of the data cache ACET for 34 models. In 16 of 36 cases, the SMMU WCET is better than the data cache ACET.

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Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors

Cited by 10 publications

References 15 publications

A Predictable Execution Model for COTS-Based Embedded Systems

A Predictable Execution Model for COTS-Based Embedded Systems

Time-based intrusion detection in cyber-physical systems

Investigating Average versus Worst-Case Timing Behavior of Data Caches and Data Scratchpads

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