Metal-Assisted Solid-Phase Crystallization Process for Vertical Monocrystalline Si Channel in 3D Flash Memory

Miyagawa, Hiroomi; Fujiwara, M.; Mitani, Yuichiro; Tomoyuki, Obu; Aochi, Hideaki; Kusai, Haruka; Takaishi, Riichiro; Tomoya, Kawai; Kamimuta, Yuuichi; Murakami, Toshiya; Ariyoshi, Kingo; Asano, Tanemasa; Goto, Masakazu

doi:10.1109/iedm19573.2019.8993556

Cited by 21 publications

(7 citation statements)

References 4 publications

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“…Therefore, a solid‐phase crystallization (SPC) process was suggested recently, as described in Figure . [ 127 ] In this SPC, the metal Ni was deposited on the exposed channel amorphous Si and allowed to react to form the Ni‐silicide. Then, the remaining Ni metal was wet‐etched away, and the wafer was annealed to drive the Ni‐silicide down to the bottom of the channel hole c , leaving behind the single‐crystalline Si channel.…”

Section: New Process and Materials Technologies To Meet Several Chall...mentioning

confidence: 99%

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Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176‐layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate vs charge‐trap‐layer), array‐level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell‐level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

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Section: New Process and Materials Technologies To Meet Several Chall...mentioning

confidence: 99%

mentioning

confidence: 99%

Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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“…The benefit of increasing ratio in storing capacity also decreases as several bit increase. The metal-assisted solid-phase crystallization process [7] is one of the promising technology to improve V th variability as shown in Fig. 6 and expands multi-bit capability further.…”

Section: A Memory Cell Technologymentioning

confidence: 99%

Flash Memory and Its Manufacturing Technology for Sustainable World

Ishimaru¹,

Fujiwara²,

Miyagawa³

et al. 2022

IEEE J. Electron Devices Soc.

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In today's data-driven society, memory is an unavoidable component. IoT and 5G are accelerating data generation exponentially, and the demands of high-capacity memory are increasing. Flash memory is a crucial infrastructure component and inevitable for Data Center. The advantages of a Solid-State Drive over a Hard Disk Drive are power consumption and volume per giga-byte. Low power consumption of storage devices, which are components of the data center itself, is critical in reducing power consumption, which has become a primary social concern. This paper describes current efforts and future trends in storage devices and their manufacturing technologies for realizing a sustainable society. New device structure which increases storage capacity with significant reduction of both materials and process steps, environmentally friendly and efficient manufacturing technologies and future technologies under consideration for even higher capacity will be shown. These technological innovations will make it possible to realize a society that enriches people's lives.

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“…Beyond HLC, to achieve 7-bit per cell (7LC) or 8-bit per cell (8LC or OLC), cell Vth distribution needs to be much smaller. The read noise may be lowered by the singlecrystal channels [35]- [37] or new channel materials. The data retention characteristics are known to be better for the floating gate (FG) type than the CT type [38], and there is still room to optimize the tunneling oxide layer for extremely low temperatures.…”

Section: E Multilevel Cell and 6-bit Per Cellmentioning

confidence: 99%

Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling

Sanuki¹,

Aiba²,

Tanaka³

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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This report introduces the cryogenic operation and storage performance of 3-D flash memory. The cell transistor characteristics and the basic functionalities, including read and program and erase (P/E) operations, are investigated at an extremely low temperature of 77 K cooled by the liquid nitrogen. The cell transistor has a steep subthreshold slope at 77 K compared with at 300 K, and the read operation is fully functional even though the saturation current becomes relatively small. P/E operations at 77 K are not much different from those at 300 K, and the same incremental-step pulse programming (ISPP) and incremental-step pulse erase (ISPE) methods are applicable. In addition, the storage performance and the reliability characteristics of 3-D flash memory, such as the read noise, the disturb characteristics, the data retention, and the cycle endurance, are also investigated. While there is no degradation in the disturb characteristics, the read noise at 77 K was significantly minimized compared with that at 300 K. The data retention characteristics are about three times improved, and the cycle endurance is about ten times improved at 77 K compared with at 300 K. These storage performance improvements and high-reliability characteristics at cryogenic operation enable us to achieve the ultramultilevel cell. We show the successful demonstration of 6-bit per cell (HLC) and discuss the impact of additional cooling cost and the possibility of future storage devices beyond HLC. The cryogenic operation of 3-D flash memory can greatly improve the storage performance and opens the door for potential new applications and the bit cost scaling for future storage devices.INDEX TERMS 3-D flash memory, 6-bit per cell (HLC), 77 K, bit cost scaling, cryogenic, immersion cooling, liquid nitrogen, NAND.

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Metal-Assisted Solid-Phase Crystallization Process for Vertical Monocrystalline Si Channel in 3D Flash Memory

Cited by 21 publications

References 4 publications

Review of Semiconductor Flash Memory Devices for Material and Process Issues

Review of Semiconductor Flash Memory Devices for Material and Process Issues

Flash Memory and Its Manufacturing Technology for Sustainable World

Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling

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