Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation

Khan, Anam; Loan, Sajad A.

doi:10.1007/s12633-020-00528-9

Cited by 8 publications

(3 citation statements)

References 23 publications

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“…It is can be concluded from Table 2 that the proposed structure provides best optimized ambipolar suppression. The OGD‐TFET, DE HTFET, 42 and MD‐HTFET 43 provide only partial suppression. Besides, OGD‐HTFET and MD‐HTFET exhibit much higher capacitances and MD‐OGD‐HTFET impact the ON current severely.…”

Section: Resultsmentioning

confidence: 99%

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

Haris

Loan

Mainuddin

2020

Int J Numerical Modelling

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In this work, we present the design and simulation of a novel structure of In0.53Ga0.43As/InP based hetero junction tunnel field effect transistor (HTFET). The proposed HTFET employs two gates: the conventional main gate and a pseudo split gate (PSG) at the drain side. The PSG is placed at the top of the drain region with the same equivalent oxide thickness (EOT) and work function as that of the main gate at an optimized separation from gate electrode. The PSG is not an active gate and it is not connected to either VDD or gate voltage. Two dimensional simulation study has revealed that the proposed device suppresses ambipolar current by ~10 orders of magnitude as compared to a HTFET without overlap and by >7 orders as compared to overlapping gate on drain HTFET (OGD‐HTFET). The PSG‐based HTFET (PSG‐HTFET) also exhibits lesser total gate capacitance as compared to OGD TFET. The proposed PSG‐HTFET offers much better ambipolar suppression even at higher drain doping and lower EOT, as compared to OGD‐HTFET. Further, the PSG‐HTFET exhibits 50% and 40% lesser fall and rise propagation delays respectively as compared to the OGD‐HTEFT. Further, the voltage overshoot and undershoot have also been suppressed in the proposed PSG‐HTFET. The scalability analysis shows that the PSG‐HTFET has better scalability in terms of ambipolar suppression, total gate capacitance, and propagation delays.

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Section: Resultsmentioning

confidence: 99%

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

Haris

Loan

Mainuddin

2020

Int J Numerical Modelling

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“…Charge diffusion from the source to channel makes it difficult to establish abrupt junctions in TFETs, which results in random dopant fluctuations and lower device performance. − These are just a few of the challenges that TFET encounters. Additionally, the low ON current ( I ON ) and enhanced ambipolarity of TFETs reduce their sensitivity and limit their usage in real-time applications. − Numerous VTFET configurations incorporate dual sources to address ambipolarity issues, thereby reducing leakage current and enhancing device performance. , Little progress has been achieved in developing complex TFET device topologies using current CMOS manufacturing techniques, despite attempts to boost the TFET sensitivity by structural alterations. This study intends to investigate the benefits of reduction of OFF current ( I OFF ) and subthreshold swing (SS) in MOSFETs that has previously been accomplished using negative capacitance (NC), utilizing the inherent characteristics of ferroelectric (FE) oxide materials.…”

Section: Introductionmentioning

confidence: 99%

“…18−21 Numerous VTFET configurations incorporate dual sources to address ambipolarity issues, thereby reducing leakage current and enhancing device performance. 22,23 Little progress has been achieved in developing complex TFET device topologies using current CMOS manufacturing techniques, despite attempts to boost the TFET sensitivity by structural alterations. This study intends to investigate the benefits of reduction of OFF current (I OFF ) and subthreshold swing (SS) in MOSFETs that has previously been accomplished using negative capacitance (NC), utilizing the inherent characteristics of ferroelectric (FE) oxide materials.…”

Section: Introductionmentioning

confidence: 99%

Assessment of the Biosensing Capabilities of SiGe Heterojunction Negative Capacitance-Vertical Tunnel Field-Effect Transistor

Singh,

Agnihotri,

Bagga

et al. 2024

ACS Appl. Bio Mater.

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In this study, a comparison of the negative capacitance vertical tunnel field-effect transistor (NC-VTFET) and VTFET for biosensing applications was conducted. Dielectrically modulated TFET demonstrates better sensitivity than the traditional metal oxide field effect transistor as a biosensor in label-free biosensing applications. The TFET biosensor, however, has much room for advancement by enhancing its DC characteristics. This research addresses the impact of ferroelectric gate oxide for integration of negative capacitance (NC) effect with the SiGe heterojunction pocket at the source–channel junction to enhance performance for biosensor applications. By putting the NC layer over SiO2, the channel voltage increases with decreased subthreshold slope and OFF current, thereby creating an NC effect. Because SiGe has a narrow band gap, pocket doping of SiGe near the source channel junction will increase the concentration of charge carriers, improving the band-to-band tunneling. In order to aid in the integration of biomolecules and to modulate band-to-band tunneling based on charge density (q f), dielectric constant (k), temperature, and cavity length, a cavity is additionally inserted above the source channel junction and underneath the NC layer, near to SiO2. These values were compared with and without the incorporation of NC layer with respect to various electrical properties such as drain current (I d), sensitivity, and electric field (E). According to the findings, labeled and label-free biosensors’ sensitivity may be increased by incorporating the NC effect into VTFET biosensors.

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Germanium Source Metal Drain Tunnel FET with Dual Dielectric Underlap

Khan

Alkhammash

Loan

2021

Silicon

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Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation

Cited by 8 publications

References 23 publications

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

Assessment of the Biosensing Capabilities of SiGe Heterojunction Negative Capacitance-Vertical Tunnel Field-Effect Transistor

Germanium Source Metal Drain Tunnel FET with Dual Dielectric Underlap

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Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation

Cited by 8 publications

References 23 publications

Pseudo Split Gate In0.53Ga0.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

Pseudo Split Gate In0.53Ga0.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

Assessment of the Biosensing Capabilities of SiGe Heterojunction Negative Capacitance-Vertical Tunnel Field-Effect Transistor

Germanium Source Metal Drain Tunnel FET with Dual Dielectric Underlap

Contact Info

Product

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About

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis