Metal-Ferroelectric-Meta-Oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification

Rusu, Alexandru; Salvatore, Giovanni A.; Jiménez, David; Ionescu, Adrian M.

doi:10.1109/iedm.2010.5703374

Cited by 141 publications

(147 citation statements)

References 3 publications

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“…However, the TFET low output current is the main disadvantage of this device as it may not be sufficient to drive the circuit capacitors. It should be noted that besides the ability of ferroelectrics for data storage, ferroelectric transistors also benefits from the ferroelectrics negative capacitance effect that amplifies the surface potential and boosts the output current [41,42]. In Fig.…”

Section: Nanometer Scale Fe-tfetmentioning

confidence: 99%

Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

Saeidi

Biswas

Ionescu

2016

Solid-State Electronics

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a b s t r a c tThe implementation and operation of the nonvolatile ferroelectric memory (NVM) tunnel field effect transistors with silicon-doped HfO 2 is proposed and theoretically examined for the first time, showing that ferroelectric nonvolatile tunnel field effect transistor (Fe-TFET) can operate as ultra-low power nonvolatile memory even in aggressively scaled dimensions. A Fe-TFET analytical model is derived by combining the pseudo 2-D Poisson equation and Maxwell's equation. The model describes the Fe-TFET behavior when a time-dependent voltage is applied to the device with hysteretic output characteristic due to the ferroelectric's dipole switching. The theoretical results provide unique insights into how device geometry and ferroelectric properties affect the Fe-TFET transfer characteristic. The recently explored ferroelectric, silicon-doped HfO 2 is employed as the gate ferroelectric. With the ability to engineer ferroelectricity in HfO 2 thin films, a high-K dielectric well established in memory devices, the silicon-doped HfO 2 opens a new route for improved manufacturability and scalability of future 1-T ferroelectric memories. In the current research, a Si:HfO 2 based Fe-TFET with large memory window and low power dissipation is designed and simulated. Utilizing our presented model, the device characteristics of a Fe-TFET that takes full benefits from Si:HfO 2 is compared with the same devices using well-known perovskite ferroelectrics. Finally, the Fe-TFET is compared with a conventional ferroelectric memory transistor highlighting the advantages of using tunneling memory devices.

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Section: Nanometer Scale Fe-tfetmentioning

confidence: 99%

Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

Saeidi

Biswas

Ionescu

2016

Solid-State Electronics

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“…9 Especially recently, the NC effect has been increasingly investigated as it is considered one of the most promising mechanisms for overcoming the limitations of transistors. [10][11][12][13][14] In 2008, S. Salahuddin and S. Datta theorized a low-power nanoscale device that utilizes the ferroelectric NC effect to amplify gate voltage. 7 Continuing experiments on NCFETs over the past 10 years have improved this device.…”

Section: Introductionmentioning

confidence: 99%

Two-dimensional negative capacitance transistor with polyvinylidene fluoride-based ferroelectric polymer gating

Wang

Chen

et al. 2017

npj 2D Mater Appl

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Conventional field-effect transistors (FETs) are not expected to satisfy the requirements of future large integrated nanoelectronic circuits because of these circuits' ultra-high power dissipation and because the conventional FETs cannot overcome the subthreshold swing (SS) limit of 60 mV/decade. In this work, the ordinary oxide of the FET is replaced only by a ferroelectric (Fe) polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)). Additionally, we employ a two-dimensional (2D) semiconductor, such as MoS 2 and MoSe 2 , as the channel. This 2D Fe-FET achieves an ultralow SS of 24.2 mV/dec over four orders of magnitude in drain current at room temperature; this sub-60 mV/dec switching is derived from the Fe negative capacitance (NC) effect during the polarization of ferroelectric domain switching. Such 2D NC-FETs, realized by integrating of 2D semiconductors and organic ferroelectrics, provide a new approach to satisfy the requirements of next-generation low-energy-consumption integrated nanoelectronic circuits as well as the requirements of future flexible electronics.

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“…The internal contact is probed (V int ) while a voltage is applied to the top gate (a zero current is injected in the internal node). As reported in [6], this probing has a negligible impact on the measurement results of the SS. Fig.…”

Section: Hysteretic Ncfetmentioning

confidence: 60%

“…A sub-thermal subthreshold swing (< ln(10)KT /q, which is 60mV /dec at T = 300K) can be obtained by decreasing the device body factor, m = 1+C s /C ins , to a value smaller than 1 (where C s and C ins are the semiconductor and the gate oxide capacitances) [3], [4]. This can be achieved by using the recently proposed negative capacitance (NC) effect of ferroelectric materials to the gate stack of conventional MOSFETs [5], [6]. It has been suggested that a Metal-Ferroelectric-Semiconductor (MFS) can provide a feasible solution to step-up the semiconductor surface potential (ψ s ) above the gate voltage (V g ) which leads to a reduction in the subthreshold swing [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation

Saeidi

Jazaeri

Bellando

et al. 2017

2017 47th European Solid-State Device Research Conference (ESSDERC)

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Abstract-This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative capacitance effect. In hysteretic devices, subthreshold slope as steep as 10mV/dec is achieved in the region where the ferroelectric represents an S-shape polarization. In addition, a matching condition is achieved between a PZT capacitor and the gate capacitance of MOSFETs fabricated on SOI substrates. For the first time, we achieve a non-hysteretic switch configuration in our fabricated MOSFETs, suitable for analog and digital applications, for which a reduction in the subthreshold swing is obtained down to 20mV/dec.

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Metal-Ferroelectric-Meta-Oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification

Cited by 141 publications

References 3 publications

Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

Two-dimensional negative capacitance transistor with polyvinylidene fluoride-based ferroelectric polymer gating

Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation

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