Metal Removal Efficiency in High Aspect Ratio Structures

Abstract

An extremely low level of metal contamination is required for specific devices like memories and CMOS Image sensors. Most of past work in the literature has focused on blanket wafer decontamination, since metrology is mostly adapted to flat surfaces. Metal removal efficiency has been compared between blanket wafers versus high aspect ratio deep trenches wafers. Two different metrology technics enable a quantitative and spatial metal removal determination on patterned wafers. Efficient cleaning in high aspect ratio structures requires much longer cleaning recipes than on flat surfaces.

Selective Removal of Various Resilient Ionic and Halides-Based Surface Contaminants by Wet Cleaning

“…To date, single wafer tests have been performed on Si with level contamination of 13 elements (Al, Ca, Co, Cr, Cu, Fe, Mg, Mn, Na, Ni, V, Zn) at 1E+11 at/cm². Then, VPD-ICPMS results (Figure 7), after a short process time (1 min) at 25°C in single wafer tool were very promising, with metal levels close to the lower limit of detection of all elements, making that approach better that standard diluted HCl, HF [14]. Similar results between static bath and single wafer, despite different process times, confirm the relevance of working in static baths for decontamination studies.…”

Deep Trenches Cleanliness Challenges for CMOS Image Sensors

“…This method is standard for blanket wafers but has never been tested on patterned wafers yet. Before performing some cleaning tests (10), one needs to determine the contamination uniformity: in the trenches versus the flat top surface, and in the trenches depth. Since one was wondering if the ions contamination would be uniform or not inside the trenches, a first study has been carried out to determine the contamination difference obtained between contaminated IPA versus contaminated DIW (De Ionized Water).…”