Methods to enhance the performance of Iterated Timing Analysis algorithm

Chen, Chun-Jung; Chen, Bin-Cheng; Lee, Chih-Jen; Tsai, Chen-Chi; Chou, Lin‐Na; Chang, Allen Y.

doi:10.1109/icinfa.2010.5512090

Cited by 5 publications

(2 citation statements)

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“…We perform experiments in our circuit simulator MOSTIME [4,5]. The described methods all have been implemented, including the TR integral method for FMOC, Latency-separating Scheme (LAT), Segment-picking Scheme (SP), Dynamic Segment-picking Scheme (DSP), and Inner-skipping Scheme (IS).…”

Section: Resultsmentioning

confidence: 99%

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Large-scale MOSFET and interconnect circuit simulation using iterated timing analysis and transmission line time step control

Chen

2011

SPIE Proceedings

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In modern circuit design community, to perform large-scale circuit simulation for MOSFET and interconnect circuits is an important subject. This paper presents an efficient and robust way to satisfy this requirement. It uses ITA (Iterated Timing Analysis) algorithm, serving as the main algorithm, and a transmission line calculation algorithm, serving as the interconnect calculator, to do the simulation task. More important, accelerating methods to fasten both ITA and the transmission line calculator also proposed in this paper. All presented methods have been implemented and tested to justify their efficiency and robustness.

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Section: Resultsmentioning

confidence: 99%

“…We overcome this disadvantage by developing an accelerating method based on latency-checking technique [5]. Also, the original FMOC uses dense and fixed inner time steps (to ensure the accuracy and numerical stability of integral method).…”

Section: Introductionmentioning

confidence: 99%