Metrology Challenges for the Ultra-thin SOI

Abstract

Future generations of CMOS technology require aggressive scaling of SOI and BOX layer thickness. This will pose significant challenges for SOI specific metrology. Future requirements for layer thickness measurements, LPD inspection, electrical and structural characterization of SOI stack are discussed. Possible directions for future development of appropriate techniques are proposed.

SOIPIX R&D programme and applications

“…Thick buried oxides present more TID effects but BOX thicknesses are decreasing, down to less than 100 nm. In advanced processes, BOX thicknesses close to 10 nm are being studied [19]. As…”