Metrology for the Electrical Characterization of Semiconductor Nanowires

Abstract

Abstract-Nanoelectronic devices based upon self-assembled semiconductor nanowires are excellent research tools for investigating the behavior of structures with sublithographic features as well as a promising basis for future information processing technologies. New test structures and associated electrical measurement methods are the primary metrology needs necessary to enable the development, assessment, and adoption of emerging nanowire electronics. We describe two unique approaches to successfully fabricate nanowire devices: one based upon harvesting and positioning nanowires and one based upon the direct growth of nanowires in predefined locations. Test structures are fabricated and electronically characterized to probe the fundamental properties of chemical-vapor-deposition-grown silicon nanowires. Important information about current transport and fluctuations in materials and devices can be derived from noise measurements, and low-frequency 1/f noise has traditionally been utilized as a quality and reliability indicator for semiconductor devices. Both low-frequency 1/f noise and random telegraph signals are shown here to be powerful methods for probing trapping defects in nanoelectronic devices.

Performance limitations for nanowire/nanoribbon biosensors

“…The justification for the scaling down of nanowire FETs and bioFETs is usually given in terms of an increased surface‐to‐volume ratio, which for the same change in surface potential would result in a larger relative signal change for the smaller cross‐section devices. However, if noise is considered, it is also well known that scaling electronic devices down to the nanoscale results in enhanced surface scattering and enhanced noise . The results shown in Figure indicate the opposite .…”

“…As electronic devices are scaled down to the nanometer regime, the larger surface‐to‐volume ratio results in enhanced scattering from surface states at the sidewalls which cause nanowires to commonly have significant current noise fluctuations . These current noise fluctuations can be analyzed in the Fourier domain and at low frequencies (typically <10,000 Hz) have the following general form: …”

“…where S I is the power spectral density of the noise (in A 2 /Hz), I is the source‐to‐drain current of the device, f is frequency, and A is a fitting parameter that depends on the noise model that is employed and essentially represents the ‘noisiness’ of the device. Hooge's model, for example, uses A = α H / N , where α H is Hooge's parameter, a noise figure of merit that is independent of measurement conditions and device geometrical characteristics . Hooge's parameter can thus be used to compare across different materials and device architectures.…”

“…Included is our best silicon‐on‐insulator ( SOI ) nanowire device (red circle). The dash‐dotted line shows the International Technology Roadmap for Semiconductors (ITRS) specification of α H for the 45‐nm technology node …”

Advanced Capacitance Metrology for Nanoelectronic Device Characterization

“…These test structures (schematically shown in Figure 6) were fabricated by using a "self-aligning" process [5,6] that has been successfully used to fabricate a variety of devices such as steepsubthreshold, Schottky tunneling FETs, [7] and charge trapping memory cells. [5,8].…”