Micro Structural Root Cause Analysis of Potential Induced Degradation in c-Si Solar Cells

Naumann, Volker; Hagendorf, Christian; Großer, Stephan; Werner, Martina; Bagdahn, J.

doi:10.1016/j.egypro.2012.07.020

Cited by 113 publications

(91 citation statements)

References 4 publications

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“…Figure 5a shows a large dark area at the center of the solar cell without a PSG layer, indicating that defects are present in that region. [14][15][16] By contrast, the solar cell containing a PSG layer had no dark area, except for metal grids (shown in Fig. 5b).…”

Section: Resultsmentioning

confidence: 99%

A Well-Controlled PSG Layer on Silicon Solar Cells against Potential Induced Degradation

Chen

et al. 2015

ECS J. Solid State Sci. Technol.

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This study proposes a promising silicon (Si) solar cell structure for reducing the potential induced degradation (PID) of crystalline Si solar cells. Phosphorous silicate glass (PSG) layers were carefully designed on an emitter layer, and the thickness of these layers (d PSG ) was controlled by adjusting the diffusion temperature and time. The results show that the power loss remarkably decreased from 31% (d PSG = 0 nm) to 11% (d PSG = 22.3 nm) and further decreased to less than 5% after a 48-h PID test when d PSG In recent years, the number of large photovoltaic (PV) systems for generating high electricity has increased. Such PV systems contain numerous high power PV modules. Therefore, the durability of a PV module is imperative.1 The potential induced degradation (PID) of crystalline silicon (Si) solar cells, first observed by Sunpower in 2005, has drawn considerable attention in recent years. [2][3][4][5][6] This is because the local electrical short-circuiting of the pn-junction in a Si solar cell occurs under high voltage stress, which leads to a substantial reduction in the power of a module. 7Several approaches can be used to prevent PID from cell to module levels. For example, leakage current can be reduced by changing the cover glass and encapsulation materials. [8][9][10] However, applying these approaches increases the cost drastically and may cause the efficiency of solar cells to deteriorate. The soda-lime cover glass and ethylene vinyl acetate (EVA) are still the most widely used and low-cost packaging materials for solar modules. Strong demand has necessitated the modification of the antireflective layers or emitter layers in PID-resistant solar cells. However, risks should be noticed that an efficiency of a solar cell and throughput may be reduced.This study proposes a promising Si solar cell structure for reducing the PID of solar cells without influencing their efficiency and throughput. Phosphorous silicate glass (PSG) layers were carefully designed on an emitter layer to determine how they affect the efficiencies of solar cells before and after PID. A current-voltage (I-V) tester was used to determine PV parameters. An ellipseometer and transmission electron microscope (TEM) were used to measure the thicknesses of the PSG layers. Secondary ion mass spectrometry (SIMS) was used to obtain concentration profiles of Si, sodium (Na), phosphorus (P), oxygen, and nitrogen. Figure 1 shows the process flow in this study as well as the structure of a solar cell with a PSG layer. Solar-grade and monocrystalline Si wafers with a size and resistivity of 5 in 2 and 0.5-3.0 ·cm, respectively, were used in this study. These wafers were processed using the following procedures: texturization by using an alkaline solution, P diffusion by using POCl 3 as a precursor, removing PSG layers by using a dilute HF solution (for standard solar cells only), depositing SixNy films as antireflection coatings by using a plasma enhanced chemical vapor deposition, and forming front and rear contacts by performing screen-p...

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Section: Resultsmentioning

confidence: 99%

A Well-Controlled PSG Layer on Silicon Solar Cells against Potential Induced Degradation

Chen

et al. 2015

ECS J. Solid State Sci. Technol.

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“…누설 전류에 의 하여 Na 이온이 태양전지 표면까지 이동하게 되는 상 황을 예상할 수 있고 이 관점에서 Na 이온의 PID 영향 성에 대한 연구가 진행되고 있다. [13][14][15][16][17][18][19] J. Bauer, V. Naumann 등은 모듈에 전압을 인가한 후 Time-of-flight Secondary ion mass spectroscopy(ToF-SIMS)를 이용하여 PID 이후 Na 이온에 의해 에미터 특 성이 변할 수 있음을 제안하였다. ( Fig.…”

Section: )unclassified

Potential Induced Degradation(PID) of Crystalline Silicon Solar Modules

Bae¹,

Oh²,

Kim³

et al. 2014

Korean. J. Mater. Res.

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The use of solar energy generation is steadily increasing, and photovoltaic modules are connected in series to generate higher voltage and power. However, solar panels are exposed to high-voltage stress (up to several hundreds of volts) between grounded module frames and the solar cells. Frequent high-voltage stress causes a power-drop in the modules, and this kind of degradation is called potential induced degradation (PID). Due to PID, a significant loss of power and performance has been reported in recent years. Many groups have suggested how to prevent or reduce PID, and have tried to determine the origin and mechanism of PID. Even so, the mechanism of PID is still unclear. This paper is focused on understanding the PID of crystalline-silicon solar cells and modules. A background for PID, as well as overviews of research on factors accelerating PID, mechanisms involving sodium ions, PID test methods, and possible solutions to the problem of PID, are covered in this paper.

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“…The non-contact, fast feedback micro-scale Na maps can also be useful in correlating highly localized regions of Na contamination to localized regions of increased potential induced degradation, PID of solar cells. 24 The technology can provide a quick feedback means for further clarification of the role of Na in two types of potential induced degradation referred to as shunting PID and polarization PID. 24 …”

Section: Surface Alkali Metalsmentioning

confidence: 99%

“…24 The technology can provide a quick feedback means for further clarification of the role of Na in two types of potential induced degradation referred to as shunting PID and polarization PID. 24 …”

Section: Surface Alkali Metalsmentioning

confidence: 99%

Non-Visual Defect Monitoring with Surface Voltage Mapping

Findlay¹,

Marinskiy²,

Edelman³

et al. 2015

ECS J. Solid State Sci. Technol.

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Non-Visual Defects (NVD) is a category of semiconductor material and process induced defects that cause electrical failures, but are not detected with visual wafer inspection tools. This paper gives an overview of our non-contact electrical NVD metrology that uses fast whole wafer inspection with standard mm resolution Kelvin probe surface voltage mapping. In an advanced approach detected NVDs are mapped in high resolution (μm range) using Force Kelvin Probe Microscopy. In depth NVD characterization is done with the corona-Kelvin method that quantifies dielectric and interfacial properties in the defect site. This characterization is performed in a non-invasive fluence range of corona charging and all measurements are non-contact, and do not require fabrication of test devices. Wafer inspection based on surface voltage mapping is used in silicon IC processing for detection of a broad category of defects that are revealed on the surface as localized regions with different values of surface potential. The approach has been very successful in monitoring of plasma etch damage [1][2][3] and was also applied to ion implant, 4,5 and wet etch process monitoring. 6 Localized charging of the silicon wafer by unbalanced plasma or an ion beam can lead to localized melting due to arcing. In less extreme cases, charging can cause antenna damage to the gate dielectric. It can also attract particles increasing surface contamination.The root cause of these electrical defects is the charging of the surface by a process that is not detected by optical based inspection tools. When the failure occurs it is not easy to troubleshoot the problem since at a later stage only the consequence of charging, but not the charging itself, is being detected. In addition to surface charge, there are other process related defects not revealed by optical inspection.In 2009 ISMI has defined non-visual defects (NVD) as a novel category of defects (novel in their classification) that cause electrical failures but do not leave behind a physical remnant that can be affordably detected with visual wafer inspection tools.7 Common NVDs also include surface metal contaminants (Cu, Fe); alkali metals (ions Na + ); and gate metal effective work function defects. In this overview we include historically important examples of surface voltage mapping, dating back to mid 1990's. Significant refinement of the technique and the improvement of map resolution and measurement speed have only recently been introduced, using multiple Kelvin probes in a novel generation of surface voltage mapping, SVM tools. 8 The corresponding most recent application examples include monitoring of defects in Si patterned wafers and high resolution intra-die mapping with microKelvin Force Probe.8 Finally, we discuss extension of the technique to epitaxial SiC layers and we compare surface voltage mapping of defects with mapping of lifetime degrading defects.9,10 The corresponding SiC results illustrate three stages of our metrology: 1-whole wafer defect mapping; 2-defect identification w...

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Micro Structural Root Cause Analysis of Potential Induced Degradation in c-Si Solar Cells

Cited by 113 publications

References 4 publications

A Well-Controlled PSG Layer on Silicon Solar Cells against Potential Induced Degradation

A Well-Controlled PSG Layer on Silicon Solar Cells against Potential Induced Degradation

Potential Induced Degradation(PID) of Crystalline Silicon Solar Modules

Non-Visual Defect Monitoring with Surface Voltage Mapping

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