Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference Methodology

Abstract

Fault injection attacks are considered one of the major threats to cyber-physical systems. The increasing complexity of embedded microprocessors involves complicated behaviours in presence of such attacks. Realistic fault models are required to study code vulnerabilities and be able to protect digital systems from these attacks. However, inferring fault models using only limited observations of faulty microprocessors is difficult. In this article, we present experiments that show the difficulty of characterizing and modelling the fault injection effects. From there, we propose a complete approach for fault analysis to build proper fault models at different system levels, which will help in designing suitable countermeasures at reasonable cost.

Cross-layer inference methodology for microarchitecture-aware fault models

“…On the basis of this evidence, we are now more confident that the gap between previous studies can be addressed by the proposed methodology [21]. This can be done by providing a cross-layer analysis of code and microarchitectural vulnerabilities while performing fault injections and simulations at three distinct levels: hardware/physical, RTL, and software levels.…”

“…In this article, which is an extended version of our work in [21], we present additional experiments for different target boards. These experiments provide additional clues for illustrating the difficulty of characterizing fault effects resulting from physical injections.…”

“…Also, different corrupted values are observed, for instance, R0 had right shift by 8, 16 or 24 bits in the first experiment, but in the second, it had only reset. In addition to that, in [21], similar target program was used for the same target board but with different registers, and some of the obtained faults were different. For example, the propagation effect on the ADD instruction of line three in Listing 1 was obvious, but this time, it is not observed for the Cortex-M4 board.…”

Variable-Length Instruction Set: Feature or Bug?

“…To perform the fault injection, a physical interference needs to be applied to the digital device. The interference can be in a form of radiations [1], laser beams [2], [3], electromagnetic (EM) pulses [4], [5], variations in the power supply [6], perturbations to the clock signal [7], [8], or changing the 1 Institute of Engineering Univ. Grenoble Alpes environmental conditions such as the temperature [9], just to cite the most widespread techniques.…”

“…The majority of the proposed fault models, in fact, describe the effects on the instruction itself: for this reason, instruction skip and instruction corruption are the most used models. In particular, the instruction skip (which can also be described as a replacement with one or more NOPs) can affect one [5], [7], [8], two [8] or multiple instructions [3], [4], [10]. It is important to highlight, however, that in all of the previous works, the authors always refer to the skip model only for complete instructions, either one or more.…”