Microarchitecture optimizations for exploiting memory-level parallelism

Chou, Yuan; Fahs, Brian; Abraham, Santosh G.

doi:10.1109/isca.2004.1310765

Cited by 20 publications

(2 citation statements)

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“…The third type of models deals with cache performance based on data flows across the memory hierarchy. Memory Level Parallelism (MLP) has been proposed in recent years as a common memory metric [4,25,26] . MLP is the average number of outstanding long-latency main-memory accesses for each active memory access cycle.…”

Section: Related Workmentioning

confidence: 99%

“…Locality-based optimization is a well-studied topic and is the focus of data access optimization for many years (e.g., [2,3]). Techniques exploiting data concurrency or memory parallelism, such as out-of-order execution and non-blocking cache, have also been applied in modern systems to effectively overlap computation and memory accesses [4] . We posit the overall performance optimization of modern memory architectures has to combine both locality and concurrency and encompass all layers of the memory hierarchy.…”

Section: Introductionmentioning

confidence: 99%

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A Study on Modeling and Optimization of Memory Systems

Liu

Espina

Sun

2021

J. Comput. Sci. Technol.

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Accesses Per Cycle (APC), Concurrent Average Memory Access Time (C-AMAT), and Layered Performance Matching (LPM) are three memory performance models that consider both data locality and memory assess concurrency. The APC model measures the throughput of a memory architecture and therefore reflects the quality of service (QoS) of a memory system. The C-AMAT model provides a recursive expression for the memory access delay and therefore can be used for identifying the potential bottlenecks in a memory hierarchy. The LPM method transforms a global memory system optimization into localized optimizations at each memory layer by matching the data access demands of the applications with the underlying memory system design. These three models have been proposed separately through prior efforts. This paper reexamines the three models under one coherent mathematical framework. More specifically, we present a new memorycentric view of data accesses. We divide the memory cycles at each memory layer into four distinct categories and use them to recursively define the memory access latency and concurrency along the memory hierarchy. This new perspective offers new insights with a clear formulation of the memory performance considering both locality and concurrency. Consequently, the performance model can be easily understood and applied in engineering practices. As such, the memory-centric approach helps establish a unified mathematical foundation for model-driven performance analysis and optimization of contemporary and future memory systems.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%