2014 IEEE 16th Electronics Packaging Technology Conference (EPTC) 2014
DOI: 10.1109/eptc.2014.7028336
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Microbumping technology for hybrid IR detectors, 10μm pitch and beyond

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Cited by 3 publications
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“…The 65 nm CMOS technology achieved a pixel size of 50 × 50 µm 2 in the readout chip, allowing the realization of 50 × 50 µm 2 and 100 × 25 µm 2 sensor pixel cells, six times smaller than the one used in the current CMS pixel detector [7]. The ultimate limit to the size reduction due to bump-bonding is considered to be at 5-10 µm [8].…”
Section: Introductionmentioning
confidence: 99%
“…The 65 nm CMOS technology achieved a pixel size of 50 × 50 µm 2 in the readout chip, allowing the realization of 50 × 50 µm 2 and 100 × 25 µm 2 sensor pixel cells, six times smaller than the one used in the current CMS pixel detector [7]. The ultimate limit to the size reduction due to bump-bonding is considered to be at 5-10 µm [8].…”
Section: Introductionmentioning
confidence: 99%