Microcomputer bus architectures

Giuma, T.A.; Hart, K.W.

doi:10.1109/southc.1996.535106

Cited by 2 publications

(2 citation statements)

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“…In contrast to the other approaches utilizing bus topologies, (18) communication between cores is achieved via TIE queues. Such communication appears to be the fastest approach to transmitting data among physical cores.…”

Section: Methods Imentioning

confidence: 99%

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Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG

Shee

Erdos

Parameswaran

2007

Int J Parallel Prog

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Multicore processors have been utilized in embedded systems and general computing applications for some time. However, these multicore chips execute multiple applications concurrently, with each core carrying out a particular task in the system. Such systems can be found in gaming, automotive realtime systems and video / image encoding devices. These system are commonly deployed to overcome deadline misses, which are primarily due to overloading of a single multitasking core. In this paper, we explore the use of multiple cores for a single application, as opposed to multiple applications executing in a parallel fashion. A single application is parallelized using two different methods: one, a master-slave model; and two, a sequential pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues as the means of communications between two cores. In a master-slave model, we utilized a course grained approach whereby a main core distributes the workload to the remaining cores and reads the processed data before writing the results back to file. In the pipeline model, a lower * National ICT Australia is funded through the Australian Government's Backing Australia's Ability initiative, in part through the Australian Research Council. granularity is used. The application is partitioned into multiple sequential blocks; each block representing a stage in a sequential pipeline. For both models we applied a number of differing configurations ranging from a single core to a nine-core system. We found that without any optimization for the seven core system, the sequential pipeline approach has a more efficient area usage, with an area increase to speedup ratio of 1.83 compared to the masterslave approach of 4.34. With selective optimization in the pipeline approach, we obtained speed ups of up to 4.6× while with an area increase of only 3.1× (area increase to speedup ratio of just 0.68).

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Section: Methods Imentioning

confidence: 99%

“…In comparison with the interconnect network model in Refs. 10 and 11, and system bus models, (18) we develop our system using the ports and queues architecture introduced in the Xtensa LX framework. By careful design, we show that our pipeline system improves performance by approximately five times while consuming three times the area.…”

Section: Related Workmentioning

confidence: 99%