Microcontroller Based Testing of Digital IP-Core

Singh, Amandeep; Singh, Balwinder

doi:10.5121/vlsic.2012.3205

Cited by 3 publications

(3 citation statements)

References 20 publications

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“…The designers can optimize cores for their specific design needs as the Firm IP blocks are have parameterized circuit descriptions. As the parameters are flexible, it allows the designers to make the performance more predictable [9,11]. …”

Section: Firm Ipmentioning

confidence: 99%

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ASIC Implementation of I2C Master Bus Controller Firm IP Core

Sindhu¹,

Prakash²,

K.V³

2015

VLSICS

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Section: Firm Ipmentioning

confidence: 99%

“…These cores give optimized design and the highest performance for the particular physical library. The main disadvantage of hard cores is they are technology dependent and also they provide minimum flexibility and portability [9,11].…”

Section: Hard Ipmentioning

confidence: 99%

ASIC Implementation of I2C Master Bus Controller Firm IP Core

Sindhu¹,

Prakash²,

K.V³

2015

VLSICS

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“…In [Amandeep, 2012] the authors proposed a system composed by a microcontoller chip and a FPGA device that performs standard tests in the digital circuit under development. The novel feature is that there no need of test patter generator and output analyser as microcontroller performs the function of both.…”

Section: Related Workmentioning

confidence: 99%

An Integrated-Approach for Designing and Testing Specific Processors

Penteado

Moreno²,

Kofuji

2013

VLSICS

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This paper proposes a validation method for the design of a CPU on which, in parallel with the development of the CPU, it is also manually described a testbench that performs automated testing on the instructions that are being described. The testbench consists of the original program memory of the CPU and it is also coupled to the internal registers, PORTS, stack and other components related to the project. The program memory sends the instructions requested by the processor and checks the results of its instructions, progressing or not with the tests. The proposed method resulted in a CPU compatible with the instruction set and the CPU registers present into the PIC16F628 microcontroller. In order to shows the usability and success of the depuration method employed, this work shows that the CPU developed iscapable of running real programs generated by compilers existing on the market. The proposed CPU was mapped in FPGA, and using Cadence tools, was synthesized on silicon.

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