Microelectronics and photonics — the future

Suhir, Ephraïm

doi:10.1016/s0026-2692(00)00086-0

Cited by 46 publications

(18 citation statements)

References 20 publications

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“…If two neighboring lattice planes, denoted as 1 and 2, with a lattice constant a 0 , are situated in a region where an atomic concentration gradient exists, so that there are 1 …”

Section: Diffusion 21 the Diffusion Equationsmentioning

confidence: 99%

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High-resolution characterization of TiN diffusion barrier layers

Mühlbacher¹

2015

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Titanium nitride (TiN) films are widely applied as diffusion barrier layers in microelectronic devices. The continued miniaturization of such devices not only poses new challenges to material systems design, but also puts high demands on characterization techniques. To gain understanding of diffusion processes that can eventually lead to failure of the barrier layer and thus of the whole device, it is essential to develop routines to chemically and structurally investigate these layers down to the atomic scale. In the present study, model TiN diffusion barriers with a Cu overlayer acting as the diffusion source were grown by reactive magnetron sputtering on MgO(001) and thermally oxidized Si(001) substrates. Cross-sectional transmission electron microscopy (XTEM) of the pristine samples revealed epitaxial, single-crystalline growth of TiN on MgO(001), while the polycrystalline TiN grown on Si(001) exhibited a [001]-oriented columnar microstructure. Various annealing treatments were carried out to induce diffusion of Cu into the TiN layer. Subsequently, XTEM images were recorded with a high-angle annular dark field detector, which provides strong elemental contrast, to illuminate the correlation between the structure and the barrier efficiency of the single- and polycrystalline TiN layers. Particular regions of interest were investigated more closely by energy dispersive X-ray (EDX) mapping. These investigations are completed by atom probe tomography (APT) studies, which provide a three-dimensional insight into the elemental distribution at the near-interface region with atomic chemical resolution and high sensitivity. In case of the single-crystalline barrier, a uniform Cu-enriched diffusion layer of 12 nm could be detected at the interface after an annealing treatment at 1000 °C for 12 h. This excellent barrier performance can be attributed to the lack of fast diffusion paths such as grain boundaries. Moreover, density-functional theory calculations predict a stoichiometry-dependent atomic diffusion mechanism of Cu in bulk TiN, with Cu diffusing on the N-sublattice for the experimental N/Ti ratio. In comparison, the polycrystalline TiN layers exhibited grain boundaries reaching from the Cu-TiN interface to the substrate, thus providing direct diffusion paths for Cu. However, the microstructure of these columnar layers was still dense without open porosity or voids, so that the onset of grain boundary diffusion could only be found after annealing at 900 °C for 1 h. The present study shows how to combine two high resolution state-of-the-art methods, TEM and APT, to characterize model TiN diffusion barriers. It is shown how to correlate the microstructure with the performance of the barrier layer by two-dimensional EDX mapping and three-dimensional APT. Highly effective Cu-diffusion barrier function is thus demonstrated for single-crystal TiN(001) (up to 1000 °C) and dense polycrystalline TiN (900 °C)

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“…If two neighboring lattice planes, denoted as 1 and 2, with a lattice constant a 0 , are situated in a region where an atomic concentration gradient exists, so that there are 1 …”

Section: Diffusion 21 the Diffusion Equationsmentioning

confidence: 99%

“…Still, the drive for smaller, faster, more reliable and less expensive ICs with more diverse functionality has not let up. A common measure of progress in IC design is the degree of device miniaturization [1]. The transition towards the 10 nm technology node [2] poses new challenges to materials scientists and reliability engineers alike.…”

Section: Introductionmentioning

confidence: 99%

High-resolution characterization of TiN diffusion barrier layers

Mühlbacher¹

2015

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“…Flip chip interconnection involves the assembly of naked, unpackaged chips directly to a supporting board, requiring products to be manufactured with solder joints at geometries similar to those of the semiconductor chips. Further reduction in the scale of flip chip geometries is expected, to ensure the technology keeps abreast of future product applications and integrated circuit (IC) designs [1], [2]. Such demands are also reflected at the board level, where microvia technology Manuscript received September 13, 2005; revised November 9, 2005.…”

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confidence: 99%

Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection

Liu

Hendriksen²,

Hutt

et al. 2006

IEEE Trans. Comp. Packag. Technol.

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Abstract-New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects.Index Terms-Flip-chip, shear Strength, stencil Printing, under bump metallization (UBM).

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“…The most typical loads are thermal loads. These are caused by CTE mismatch and/or by temperature gradients [1][2][3][4][5][6][7][8].…”

Section: Thermal Loading and Thermal Stress Failuresmentioning

confidence: 99%

“…The most typical loads are thermal loads. These are caused by CTE mismatch and/or by temperature gradients [1][2][3][4][5][6][7][8].Thermal loading takes place during the normal operation of the system, as well as during its fabrication, testing, or storage. Thermal stresses, strains and displacements are the major contributor to the finite service life and elevated failure rate of ME and OE equipment.…”

mentioning

confidence: 99%

Analytical Thermal Stress Modeling in Physical Design for Reliability of Micro- and Opto-Electronic Systems: Role, Attributes, Challenges, Results

Suhir

Micro- And Opto-Electronic Materials and Structures: Physics, Mechanics, Design, Reliability, Packaging

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"Mathematical formulas have their own life, they are smarter than we, even smarter than their authors, and provide more than what has been put into them"Heinrich Hertz, German Physicist "If my theory is in conflict with the experiment, I pity the experiment", Friedrich Hegel, German Philisopher"A formula longer than three inches is most likely wrong" Unknown Reliability Engineer ABSTRACTSome basic thermal stress and thermal stress related reliability problems in microelectronics (ME) and optoelectronics (OE) are addressed. The emphasis is on analytical ("mathematical") stress modeling and design for reliability. The review is based primarily on the author's research conducted during his eighteen-year tenure with Bell Laboratories, Basic Research, Physical Sciences and Engineering Research Division, as well as on his recent research, based on government contracts. THERMAL LOADING AND THERMAL STRESS FAILURESVarious areas of engineering differ, from the Structural Analysis and Structural Reliability point of view, by the employed materials, typical structures used, and the nature of the applied loads. The most typical ME and OE structures are bodies made of a large variety of dissimilar materials. The most typical loads are thermal loads. These are caused by CTE mismatch and/or by temperature gradients [1][2][3][4][5][6][7][8].Thermal loading takes place during the normal operation of the system, as well as during its fabrication, testing, or storage. Thermal stresses, strains and displacements are the major contributor to the finite service life and elevated failure rate of ME and OE equipment. Examples are ductile rupture, brittle fracture, thermal fatigue, creep, excessive deformation or displacement, stress relaxation (that might lead to excessive displacements), thermal shock, stress corrosion.Elevated thermal stresses and strains can lead not only to structural ("physical") failure, but also to functional (electrical or optical) failure. If the heat, produced by the chip, cannot readily escape, then the high thermal stress in the IC can result in failure of the p-n junction [9]. Low temperature microbending (buckling of the glass fiber within the low modulus primary coating) in dual-coated optical fibers, although might be too small to lead to appreciable bending stresses and delayed fracture ("static fatigue"), can result in appreciable added transmission losses. Loss in optical coupling efficiency can occur, when the displacement in the lateral (often less than 0.2 micrometers) or angular (often less than a split of one percent of a degree) misalignment in the gap between two light-guides or between a light source and a light-guide becomes too large, because of thermally induced deformations or because of thermal stress relaxation in a laser weld. Small lateral or angular displacements in MEMS-based photonic systems (such as, say, some types of tunable lasers) can lead to a complete optical failure of the device. Tiny temperature-change-induced changes in the distance between Bragg gratings "written" on an ...

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Microelectronics and photonics — the future

Cited by 46 publications

References 20 publications

High-resolution characterization of TiN diffusion barrier layers

High-resolution characterization of TiN diffusion barrier layers

Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection

Analytical Thermal Stress Modeling in Physical Design for Reliability of Micro- and Opto-Electronic Systems: Role, Attributes, Challenges, Results

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