Microelectronics manufacturing science and technology (MMST): single-wafer RTP-based 0.35 μm CMOS IC fabrication

Abstract

We have demonstrated the total use of single-wafer processing for fast-cycle-time IC roduction. Rapid thermal processes have been develope: for all the thermal fabrication steps required in two 0.35-pm CMOS technolo 'a. Complete CMOS rocess integration and 3-day CMObIC manufacturing cyc% time have been demonstrated with all-RTP thermal processing. Agile IC ManufacturingState-of-the-art IC factories offer high throughput rates but long manufacturing cycle times. Under the TI Microelectronics Manufacturing Science and Technology (TI-MMST) program, we launched a 5-year project in 1988 to develop a manufacturing technology with the objectives of reducin the factory cost and cycle time. Thi program has result e l i n a flexible low-cost minifactory implemented in a -5000 Jt' clean room for 0.35 pm CMOS fabrication with a recor cycle time of 3 days. 0.35-pm CMOS Process TechnologiesTwo 0.35 pm twin-well double-level metal CMOS technologies were developed with and without self-aligned silicide salicide). The non-salicided technology contains buriedchannel PMOS and surface-channel NMOS transistors and a single n+-doped polysilicon gate (75 A gate oxide). The salicided technology employs n+ and p+ polysilicon gates for the surface-channel NMOS and PMOS devices (60 A gate oxide). Fig. 1 illustrates the process modules . GAfE DESIRE IIE -n WO RTP SL R E M 3 -PO PAlTElW W Et01Figure 1: Fabrication process modules for the salicided 0.35 pm CMOS technology with surface-channel devices.for the dicided technology. The NMOS and PMOS devices employ implant-doped n+ and p+ olysilicon gates and their threshold volt es are adjuste: by the surface concentrations of the p 3 n well regions, respectively. In the non-dicided CMOS proceee flow, the NMOS threshold volta e is again directly set by the pwell concentration. The BMOS threshold voltape is, however, adjusted by a patterned low-ener y boron implant using a spht-deposited gate process (1).process eliminates the effect of gate oxidation thermal budget on the PMOS channel. RTP Equipment TechnologyThe TI-MMST minifactory contains 34 sin le-wafer rocess modules. Vacuum wafer cassettes are u s 3 for mackne for enhanced procesa uniformity. p-epi/p+ substrate I "' i 0.6 I g 0.5 0.41 0.3t 1 I -, I -n I Figure 2: Multi-sone RTP pyrometry wafer temperature measurement with light interference compensation.

Cost of silicon viewed from VLSI design perspective

“…Of course these numbers must be treated as rough estimates. The investment increase may become much higher when existing contamination and failure analysis techniques reach their limits (which is likely) or lower when projects like TI's MMST [19] deliver promised cost/contamination control benefits. c. Wafer size.…”