Microstructure Evolution and Effect on Resistivity for Cu Nanointerconnects and Beyond

Hu, Szu-Tung; Cao, Linjun; Spinella, Laura; Ho, Paul S.

doi:10.1109/iedm.2018.8614547

Cited by 6 publications

(6 citation statements)

References 2 publications

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“…This study investigated two cases: the worst case considering the array resistance and the ideal case ignoring it. The reason is, in the sub-3-nm node, a metal line had immense resistances due to the small electrical area with surface and grain boundary scattering (the worst case) [15]. However, since various SRAM assist circuit techniques [16] and methods for lowering the resistivity of BEOL materials [17] were being studied, it was necessary to analyze even the low resistance one (the ideal case).…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

et al. 2021

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For the first time, we suggested that the monolithic 3D (M3D) static random access memory (SRAM) with gate and S/D bottom contact (GBC and SDBC) schemes (SRAMSDGBC) and analyzed they could significantly improve the power, performance, and area (PPA) compared to the conventional M3D SRAM (SRAM3D). SRAM3D could not directly connect the top-tier device and the bottom-tier metal line. Thus two tiers had to be connected by bypassing the metal line. As a result, SRAM3D wasted the area to place the monolithic interlayer via and did not get 50 % area scaling. However, gate and S/D bottom contact schemes, GBC and SDBC, could solve these problems. Although these methods required additional process steps, they brought significant advantages in interconnect RC and PPA. Based on a 26 nm width nanosheet transistor, SRAM3D showed a 30 % area reduction compared to 2D SRAM (SRAM2D), whereas SRAMSDGBC showed a 50 % area reduction. In the ideal (worst) case which ignoring (considering) the array resistance, the read and write access time of SRAMSDGBC were improved 7.7 % (19 %) and 8.3 % (33 %) than SRAM3D, and the write dynamic power was improved by 5.9 % (5 %). Especially, SRAMSDGBC showed improved PPA in the worst case compared to SRAM2D_Cu, which had relatively small interconnect resistivity. Namely, GBC and SDBC schemes are essential to enhance the PPA of M3D cells and will be a promising scheme in M3D SRAM and other logic cells.

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Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

et al. 2021

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“…First, the microstucture strongly depends on the interconnect width and second, due to the increased temperatures during operation, the microstructure may undergo transformations. Experimental SEM/FIB/EBSD [27][28][29][30][31] studies of interconnects' microstructure provide the grain size distribution and the crystal orientations inside grains. These studies show that the grain sizes inside Cu interconnects are distributed according to the lognormal distribution and tend to have several predominant crystal orientations.…”

Section: Theoretical Backgroundmentioning

confidence: 99%

“…Therefore, a new method is needed to cover the typical microstructures of the nano-interconnect. 3,27 For the purpose of modeling, the interconnect metal is divided into polycrystalline and large grain domains. In the polycrystalline domains material transport is dominated by atomic migration along GBs (with the diffusivity D gb ).…”

mentioning

confidence: 99%

“…5 can be extracted from EBSD grain maps 36 and also obtained by microstructure simulations. 27 Such a representation is the basis for the extraction of ϵ s and cos q á ñ, which are required for the evaluation of expression (16).…”

mentioning

confidence: 99%

“…Since we are interested in the worst case scenario, i.e., void growing with the maximum surface velocity, for the estimation of the void evolution time t E in (27) the following expression is used:…”

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confidence: 99%

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Review—Modeling Methods for Analysis of Electromigration Degradation in Nano-Interconnects

Ceric

Selberherr

Zahedmanesh

et al. 2021

ECS J. Solid State Sci. Technol.

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Mitigation of the degradation for down-scaled interconnects requires an in-depth understanding of the failure mechanisms of electromigration and, therefore, the development of adequate simulation models based on this understanding. We present a novel concept for modeling of nano-interconnect structures, the effective domain method, which describes the impact of grain boundaries and grain distribution on the nano-interconnect reliability and how this impact changes with down-scaling of the interconnect width. Furthermore, a simple and numerically efficient approach for modeling of void growth and its influence on nano-interconnect resistivity is presented. Both novel approaches are studied on timely nano-interconnect layouts and discussed in comparison to experimental results. The simulations based on the novel modeling concept predict the reduction of interconnect lifetime with increased temperature and the reduced linewidth, as observed in experiments.

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Electromigration in Cu Interconnect Structures

2022

Electromigration in Metals

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Microstructure Evolution and Effect on Resistivity for Cu Nanointerconnects and Beyond

Cited by 6 publications

References 2 publications

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

Review—Modeling Methods for Analysis of Electromigration Degradation in Nano-Interconnects

Electromigration in Cu Interconnect Structures

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