MIMO Equalization for Multi-Gbit/s Access Nodes Affected by Manufacturing Tolerances

Abstract

Abstract-While the requirements for delivering high throughputs increase exponentially with every generation of access node hardware, the device cost is of primary concern. As a result, multiple-input multipleoutput (MIMO) equalization, which has been shown to facilitate multi-Gbit/s communication over low-cost parallel electrical interconnects, is emerging as an attractive high-speed interconnect solution for next-generation access nodes. Because of the high operating frequencies, however, the transfer functions of the on-and off-chip interconnects become highly susceptible to manufacturing tolerances (MTs); hence, the equalization filters must be adjusted to the specific channel realization to achieve optimal performance, which involves a high implementation and computational complexity. Considering that the MTs are usually limited, we propose a robust lowcomplexity transceiver consisting of a fixed MIMO linear pre-equalizer (which avoids the need for feeding back the channel state information to the transmitter), with either a fixed or adjustable MIMO decision-feedback equalizer (DFE). For a specific chip-to-chip interconnect operating at 75 Gbit/s per line and a 26 dB signal-to-noise ratio, we show that the resulting bit error rate does not exceed 10 −12 for MTs up to 10.5% (fixed DFE) and 17.7% (adjustable DFE) of the nominal line width.

On Partial Response Signaling for MIMO Equalization on Multi-Gbit/s Electrical Interconnects

“…In this work, we extended the stochastic MIMO DFE approach from [7] by setting to zero the first N taps of the feedback filters in order to relax the latency constraints on the feedback loop. PR signaling was shown to potentially enhance the performance of MIMO DFE for N > 0, by reducing the required equalization effort.…”

“…The decisionsĉ(k) are obtained by replacing u t (k) by u(k) in (2); the decisionsâ(k) at the input of the feedback filter result from applying toĉ(k) the same precoding and mapping as at the TX. Assuming the decisionsâ(k) are correct, it was shown in [7] that the decision variables u(k) are given by…”

“…With growing symbol rates, two complications are emerging: i) the channel becomes very sensitive to manufacturing tolerances, so that every interconnect has a (slightly) different impulse response, and ii) the latency in the feedback loop becomes prohibitively large. In [7], the former issue was addressed by adopting a stochastic MIMO DFE approach where (part of) the equalization filters depend on the channel statistics rather than on the actual channel, which allows to significantly reduce the computational and implementational complexity. In this contribution, we tackle the latency issue by setting to zero the first N taps of the feedback filters of a MIMO DFE scheme consisting of a fixed pre-equalizer at the TX and adjustable feedforward and feedback filters at the RX.…”