Mini-rank: Adaptive DRAM architecture for improving memory power efficiency

Zheng, Hongzhong; Jiang, Lin; Zhang, Zhao; Gorbatov, Eugene; David, Howard; Zhu, Zuqing

doi:10.1109/micro.2008.4771792

Cited by 214 publications

(159 citation statements)

References 28 publications

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“…Leveraging the observation that applications access only a few words within a cache block, researchers have proposed re-engineering the processor/memory interface to allow for activating only the DRAM chips at which the requested words are stored [1,16,58,59]. While potentially effective in the server context as well, these proposals require disruptive changes to commodity memory technology.…”

Section: Related Workmentioning

confidence: 99%

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BuMP: Bulk Memory Access Prediction and Streaming

Volos¹,

Picorel²,

Falsafi³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-With the end of Dennard scaling, server power has emerged as the limiting factor in the quest for more capable datacenters. Without the benefit of supply voltage scaling, it is essential to lower the energy per operation to improve server efficiency. As the industry moves to lean-core server processors, the energy bottleneck is shifting toward main memory as a chief source of server energy consumption in modern datacenters. Maximizing the energy efficiency of today's DRAM chips and interfaces requires amortizing the costly DRAM page activations over multiple row buffer accesses.This work introduces Bulk Memory Access Prediction and Streaming, or BuMP. We make the observation that a significant fraction (59-79%) of all memory accesses fall into DRAM pages with high access density, meaning that the majority of their cache blocks will be accessed within a modest time frame of the first access. Accesses to high-density DRAM pages include not only memory reads in response to load instructions, but also reads stemming from store instructions as well as memory writes upon a dirty LLC eviction. The remaining accesses go to low-density pages and virtually unpredictable reference patterns (e.g., hashed key lookups). BuMP employs a low-cost predictor to identify high-density pages and triggers bulk transfer operations upon the first read or write to the page. In doing so, BuMP enforces high row buffer locality where it is profitable, thereby reducing DRAM energy per access by 23%, and improves server throughput by 11% across a wide range of server applications.

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Section: Related Workmentioning

confidence: 99%

“…One way to minimize activation energy is through modifications to DRAM chips or interfaces [1,47,59]. Historically, such disruptive proposals have failed to gain traction in the DRAM industry, which is focused on commoditization and adheres to rigid standards to ensure broad compatibility.…”

Section: Introductionmentioning

confidence: 99%

BuMP: Bulk Memory Access Prediction and Streaming

Volos¹,

Picorel²,

Falsafi³

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

View full text Add to dashboard Cite

show abstract

“…The last option is to maintain a 64 bit interface and embed the ECC into the memory space instead of sitting in disparate devices [ 54,52]. The memory controller performs two accesses, one for data and one for ECC.…”

Section: Error Correction Strategiesmentioning

confidence: 99%

Towards energy-proportional datacenter memory with mobile DRAM

Malladi

Nothaft

Periyathambi

et al. 2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

181

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To increase datacenter energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high bandwidth but not for energy proportionality. A system using 20% of the peak DDR3 bandwidth consumes 2.3× the energy per bit compared to the energy consumed by a system with fully utilized memory bandwidth. Nevertheless, many datacenter applications stress memory capacity and latency but not memory bandwidth. In response, we architect server memory systems using mobile DRAM devices, trading peak bandwidth for lower energy consumption per bit and more efficient idle modes. We demonstrate 3-5× lower memory power, better proportionality, and negligible performance penalties for datacenter workloads.

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“…Numerous DDRx controller optimizations for improving performance, energy, and QoS have been published in the literature [12,13,14,15,16,32,33,34,35,36,37,41]. Unlike PARDIS, these proposals address specific workload classes (multiprogrammed, parallel, or real-time); yet a hardcoded memory controller is neither able to meet the requirements of a diverse set of applications optimally, nor can it change its objective function for a new optimization target.…”

Section: Ddrx Controller Optimizationsmentioning

confidence: 99%

PARDIS: A programmable memory controller for the DDRx interfacing standards

Bojnordi¹,

Ïpek²

2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource constraints on system performance. A promising way of improving the versatility and efficiency of these controllers is to make them programmable-a proven technique that has seen wide use in other control tasks ranging from DMA scheduling to NAND Flash and directory control. Unfortunately, the stringent latency and throughput requirements of modern DDRx devices have rendered such programmability largely impractical, confining DDRx controllers to fixed-function hardware.This paper presents the instruction set architecture (ISA) and hardware implementation of PARDIS, a programmable memory controller that can meet the performance requirements of a high-speed DDRx interface. The proposed controller is evaluated by mapping previously proposed DRAM scheduling, address mapping, refresh scheduling, and power management algorithms onto PARDIS. Simulation results show that the performance of PARDIS comes within 8% of an ASIC implementation of these techniques in every case; moreover, by enabling application-specific optimizations, PARDIS improves system performance by 6-17% and reduces DRAM energy by 9-22% over four existing memory controllers.

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Mini-rank: Adaptive DRAM architecture for improving memory power efficiency

Abstract: The widespread use of multicore processors has dramatically increased the demand on high memory bandwidth and large memory capacity. As

Cited by 214 publications

References 28 publications

BuMP: Bulk Memory Access Prediction and Streaming

BuMP: Bulk Memory Access Prediction and Streaming

Towards energy-proportional datacenter memory with mobile DRAM

PARDIS: A programmable memory controller for the DDRx interfacing standards

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