Miniaturized Double Side Cooling Packaging for High Power 3 Phase SiC Inverter Module with Junction Temperature over 220°C

Woo, Daniel Rhee Min; Yuan, Hwang How; Li, Jerry Aw Jie; Bum, Lee Jong; Zhang, Hengyun

doi:10.1109/ectc.2016.396

Cited by 29 publications

(11 citation statements)

References 2 publications

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“…Some works do not use the sandwich structure with substrate on the top of the devices. Instead conductor such as copper clip and heat pipes are used, which serve as electrical connector, as well as heat spreader [29,30]. There are also planar 2D power modules commercially available in the market with 200⁰C rating, which is from CREE (now Wolfspeed) [31].…”

Section: Planar 2d Power Package Structurementioning

confidence: 99%

3-D Prismatic Packaging Methodologies for Wide Band Gap Power Electronics Modules

Mehrotra

Hopkins

2021

IEEE Trans. Power Electron.

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Section: Planar 2d Power Package Structurementioning

confidence: 99%

3-D Prismatic Packaging Methodologies for Wide Band Gap Power Electronics Modules

Mehrotra

Hopkins

2021

IEEE Trans. Power Electron.

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“…Up to now, attempts for packaging SiC power module, e.g., planar packaging, press pack, 3-D packaging, and hybrid packaging techniques, have been performed. A. Planar Packaging Technique 1) Miniaturized Double-Side Cooling: Rhee et al [49] developed a miniaturized double-sided cooling packaging for SiC high-power inverter module using new materials to withstand high temperature over 220 • C, as shown in Fig. 25.…”

Section: Packaging Techniques For Sic Power Modulementioning

confidence: 99%

“…At present, commercially available SiC power devices are designed for Al wirebonding. The front-side pads metallization of these devices are Al, which is not compatible with wirebondless packaging techniques and an additional metallization layer is required on the front-side source and gate pads [36], [49]. Therefore, the remetallization of Al pad on the power devices is a key process for the development of wirebondless packages.…”

Section: Packaging Processmentioning

confidence: 99%

Review of Packaging Schemes for Power Module

Hou

Wang²,

Cao

et al. 2020

IEEE J. Emerg. Sel. Topics Power Electron.

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SiC devices are promising for outperforming Si counterparts in high-frequency applications due to its superior material properties. Conventional wirebonded packaging scheme has been one of the most preferred package structures for power modules. However, the technique limits the performance of a SiC power module due to parasitic inductance and heat dissipation issues that are inherent with aluminum wires. In this article, low parasitic inductance and high-efficient cooling interconnection techniques for Si power modules, which are the foundation of packaging methods of SiC ones, are reviewed first. Then, attempts on developing packaging techniques for SiC power modules are thoroughly overviewed. Finally, scientific challenges in the packaging of SiC power module are summarized.

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“…At present, commercially available SiC power devices are designed for front-side Al wire bonding. Hence, metallization layers of front-side pads on these devices are Al, which is not compatible with PCB-embedded package and an additional metallization layer is required on the front-side source and gate pads [17], [32]. Dies that had extra metallization layers are then embedded in the PCB, followed by blind vias that are usually formed by laser drilling and Cu plating, thus realizing the interconnection between dies and outer layers [14], [18], [19], [22].…”

Section: A Pid Exposure and Development Techniquementioning

confidence: 99%

Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging

Hou

Wang²,

Chen

et al. 2020

IEEE J. Emerg. Sel. Topics Power Electron.

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In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermomechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.

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Miniaturized Double Side Cooling Packaging for High Power 3 Phase SiC Inverter Module with Junction Temperature over 220°C

Cited by 29 publications

References 2 publications

3-D Prismatic Packaging Methodologies for Wide Band Gap Power Electronics Modules

3-D Prismatic Packaging Methodologies for Wide Band Gap Power Electronics Modules

Review of Packaging Schemes for Power Module

Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging

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