Minimax design of digital FIR filters using linear programming in bandwidth interleaving digital-to-analog converter

Yang, Xing; Wang, Houjun; Liu, Ke; Xiao, Yegui; Fu, Zaiming; Guo, Guo

doi:10.1587/elex.15.20180565

Cited by 11 publications

(79 citation statements)

References 12 publications

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“…It could be regarded as a perfect reconstruction HFB system. Several studies have been published focus on the design of perfect reconstruction [25,26,27]. If the timing mismatch error occurred, x ′ m (t) =x m (t − ∆t m ).…”

Section: Hybrid-filter-bank Dac With Timing Mismatchmentioning

confidence: 99%

“…Since the mismatch errors of filter banks significantly degrade the system performance [20,21,22,23]. Many studies [24,25,26,27] focus on the perfect reconstruction design of filter banks while the mismatch estimation and calibration are relatively less studied. In [28], a pre-compensation method for mixers mismatch error in HFB DAC is proposed.…”

Section: Introductionmentioning

confidence: 99%

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An estimation method of timing mismatch error in hybrid filter bank DACs

Yin

Tian

Liu

et al. 2020

IEICE Electron. Express

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This paper presents an estimation method of timing mismatch error in hybrid filter bank digital-to analog converter (HFB DAC). An approximated transfer function of HFB DAC with timing mismatch is derived based on the Taylor series. Then an iteration method is introduced to approach the timing error. Besides, we analyze the influence of test signal and give the requirements on test input. Using this signal, the iteration will have a fast convergence speed. Simulation experiments show the effectiveness of the proposed estimation method.

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Section: Hybrid-filter-bank Dac With Timing Mismatchmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An estimation method of timing mismatch error in hybrid filter bank DACs

Yin

Tian

Liu

et al. 2020

IEICE Electron. Express

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“…Bandwidth interleaving (BI) DAC [5]- [11], not affected by the ZOH characteristic of each sub-DAC, could be also used as the other method to break through the DAC output bandwidth limitation such that the available signal bandwidth can be increased. Fig.1 shows an architecture of BI-DAC with M sub-DACs, the bandwidth of the BI-DAC analog wideband output y (t) is increased M times each sub-DAC output bandwidth.…”

Section: Introductionmentioning

confidence: 99%

“…We can know from [11], in a BI-DAC with M sub-DACs shown in Fig.1, digital finite impulse response (FIR) filters F m (z) , m = 1, . .…”

Section: Introductionmentioning

confidence: 99%

Minimax and WLS Designs of Digital FIR Filters Using SOCP for Aliasing Errors Reduction in BI-DAC

et al. 2019

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This paper presented the optimal minimax and weighted least squares (WLS) methods for designing digital finite impulse response (FIR) filters to reduce the aliasing errors generated by the non-ideality of analog filters and mixers in bandwidth interleaving digital-to-analog converter (BI-DAC). To satisfy the given expected spurious free dynamic range (SFDR), we formulated these optimal designs of digital FIR filters in BI-DAC as a convex optimization problem-second-order cone programming (SOCP) that allowed the linear equality and convex quadratic inequality constraints including the magnitude flatness and the peak aliasing errors constraints to be merged. Furthermore, we derived the computational complexity of our presented optimal design. Several design examples were given to evaluate the performance of our presented unconstrained and constrained minimax and WLS designs using SOCP including their effectiveness and computational complexity. The simulation results showed that, in our presented unconstrained minimax and WLS designs using SOCP, the maximum distortion errors were all around 0.02 dB. The maximum aliasing errors were−73.9 and −80.5 dB, which satisfied the expected SFDR of a 12-bit BI-DAC system. In addition, we analyzed the influence of different values of the nonnegative weighting function on our presented unconstrained minimax and WLS designs using SOCP, and we found that there was a tradeoff among the nonnegative weighting function's value, and the distortion and aliasing errors. Moreover, when the constraints were imposed in our presented constrained minimax and WLS designs using SOCP in the selected frequency bands, the distortion errors were equal to zero and the aliasing errors were reduced below −110 dB, but the expense was that the larger distortion and aliasing errors achieved out of these selected frequency bands. Finally, we gave the computational complexity comparisons among our presented unconstrained and constrained minimax and WLS design using SOCP, we also compared the influence of the digital FIR filters' length on our presented designs' worst-case passband ripple and stopband roll-off, and we found that there was a tradeoff among the digital FIR filters' length, the passband ripple, the stopband roll-off, the computational complexity, and the actual hardware cost. INDEX TERMS Minimax and weighted least squares (WLS) designs, digital FIR filter, second-order cone programming (SOCP), aliasing errors reduction, linear equality and convex quadratic inequality constraints.

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“…The HFB system suffer from the aliasing error if the analysis filters and synthesis filters are not well matched [17,18,19,20,21]. Several filter match design methods such as linear programming [22], second-order cone programming [23] have been proposed to eliminate the aliasing error and minimize the distortion. Most works [24,25,26,27,28,29] focus on designing the digital filter to match a pre-set analog filter bank while the parameter of these analog filters are not discussed.…”

Section: Introductionmentioning

confidence: 99%

Optimization of synthesis filters for hybrid filter bank DACs

Yin

Tian

Liu

et al. 2019

IEICE Electron. Express

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Hybrid filter bank (HFB) is a promising technology that both improve the resolution and speed of digital-to-analog conversion. In this letter, we present a wideband waveform generation method using HFB architecture. Mixers are adopted to break through the limitation caused by zero-order-hold (ZOH) of DACs. However, the imperfect match of analysis filters and synthesis filters significantly degrade the system performance. To solve this problem, we analyze the influence of filter mismatch. An analysis filter design based on weighted least squares (WLS) and an optimization design for synthesis filter is presented. The optimization method invokes the WLS method at each iteration. Performance evaluation shows that these two methods work together and perform a better reconstruction system than the WLS method which just focus on analysis filter bank.

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Minimax design of digital FIR filters using linear programming in bandwidth interleaving digital-to-analog converter

Cited by 11 publications

References 12 publications

An estimation method of timing mismatch error in hybrid filter bank DACs

An estimation method of timing mismatch error in hybrid filter bank DACs

Minimax and WLS Designs of Digital FIR Filters Using SOCP for Aliasing Errors Reduction in BI-DAC

Optimization of synthesis filters for hybrid filter bank DACs

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