Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

Nguyen, David H.; Davare, Abhijit; Orshansky, Michael; Chinnery, David; Thompson, Brandon L.; Keutzer, Kurt

doi:10.1145/871540.871545

Cited by 38 publications

(54 citation statements)

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“…Supply and threshold voltage optimization, in the context of low power CMOS circuit design, is an area of active current research; see, e.g., Anis et al (2003), Chabini et al (2003), Chen et al (2001), Kao et al (2002), Pant et al (2001), and Srivastava and Sylvester (2004). Many approaches to low power CMOS design have been proposed in the literature, including design with multiple supply and threshold voltages (Chang and Pedram 1997;Jung et al 2003;Kim et al 2003a, b;Krishnamurthy and Carley 1997;Marković et al 2004;Sirichotiyakul et al 2002;Srivastava and Sylvester 2004;Yeh et al 2001), multiple threshold CMOS (MTCMOS) (Anis et al 2002(Anis et al , 2003Calhoun et al 2004;Kao and Chandrakasan 2000), variable threshold CMOS (VTCMOS) via adaptive body biasing (Im et al 2003, Kao et al 2002, Tschanz et al 2003, Yang et al 1997, dynamic threshold CMOS (DTCMOS) (Assaderaghi et al 1997), joint device sizing and V dd /V th assignment (Augsburger and Nikolić 2002a, b;Chen and Sarrafzadeh 2002;Hung et al 2004;Ketkar and Sapatnekar 2002;Karnik et al 2002;Liu et al 2004;Nguyen et al 2003;Pant et al 2001), dynamic frequency scaling (Lu et al 2002), supply voltage scaling (Bellaouar et al 1998), and transistor stacking (Johnson et al 2002.…”

Section: Supply and Threshold Voltage Optimizationmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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Section: Supply and Threshold Voltage Optimizationmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

154

146

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“…This fact pushed designers to search for new methods to grant low power consumption for video processing applications. Many solutions have been proposed as an attempt to minimize both static and dynamic energy for video applications [2][3][4] and, although having reached a remarkable percentage, the obtained results remain insufficient and need more improvements. Therefore, power consumption should be added as a major constraint to be optimized.…”

Section: Introductionmentioning

confidence: 99%

Design of low power system on programmable chip for video zoom-in processing

Touil¹,

Kechiche²,

Ouni³

2016

Turk J Elec Eng & Comp Sci

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Today, power consumption presents a critical issue when designing embedded systems. It has become a key factor in a product's success when being marketed, especially for mobile systems. In this paper, we have developed a typical design for video zoom-in processing with low power consumption. The proposed design has been implemented on the Xilinx Virtex-5 with the integration of different important resources like embedded processor, embedded memory, MPMC, DDR, and various interfaces. The design results show a significant gain in power at the simulation level as well as the physical one. In addition, the proposed design provides an important gain in power without degrading other parameters such as frequency, area, and others.

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“…Dual-V th assignment [2][3][4][5][6] is an efficient technique to decrease leakage power. Wei et al [3] describe an algorithm to find the optimal high V th for different circuit structure.…”

Section: Introductionmentioning

confidence: 99%

“…On the contrary, using ILP, a global optimization solution can be easily achieved. Nguyen et al [6] use linear programming (LP) to minimize the leakage and dynamic power by gate sizing and dual-threshold voltage devices assignment. However, they have not considered the glitch power, which can account for 20%-40% of the dynamic switching power [7].…”

Section: Introductionmentioning

confidence: 99%

Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing

Agrawal

2005

Lecture Notes in Computer Science

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Abstract. This paper presents a novel technique, which uses integer linear programming (ILP) to minimize the leakage power in a dual-threshold static CMOS circuit by optimally placing high-threshold devices and simultaneously reduces the glitch power using the smallest number of delay elements to balance path delays. The constraint set size for the ILP model is linear in the circuit size. Experimental results show 96%, 40% and 70% reduction of leakage, dynamic and total power, respectively, for the benchmark circuit C7552 implemented in the 70nm BPTM CMOS technology.

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Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

Cited by 38 publications

References 0 publications

Digital Circuit Optimization via Geometric Programming

Digital Circuit Optimization via Geometric Programming

Design of low power system on programmable chip for video zoom-in processing

Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing

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