Minimization of germanium penetration, nanocrystal formation, charge storage, and retention in a trilayer memory structure with silicon nitride/hafnium dioxide stack as the tunnel dielectric

Abstract

Trilayer structures, consisting of a rapid thermal oxide (RTO) layer (2.5 or 5 nm thick) grown on silicon, a sputtered Ge middle layer (3–20 nm thick), and a 50-nm-thick sputtered silicon oxide capping layer, exhibit significant penetration of Ge atoms into the silicon substrate for devices with the smaller (2.5 nm) RTO thickness, resulting in negligible nanocrystal formation and hence no charge storage or memory effect. The Ge penetration is minimized by replacing the RTO layer with a high dielectric constant (high-κ) silicon nitride/hafnium dioxide stack (grown by metalorganic chemical vapor deposition) having a larger physical thickness but smaller equivalent oxide thickness of 1.9 nm. Results show that the high-κ trilayer structure exhibits better charge storage capability (in terms of a lower program voltage) and better charge retention performance as compared to the RTO trilayer structure.

Enhanced memory performance by tailoring the microstructural evolution of (ZrO2)0.6(SiO2)0.4 charge trapping layer in the nanocrystallites-based charge trap flash memory cells

“…As a high-k dielectric, ZSO allows a higher electric field cross the tunneling layer due to electric flux density continuity [14], and results in a modified Fowler-Nordheim tunneling due to the smaller conduction band offset (CBO) with a Si substrate [15]. In addition, high-k dielectrics Al 2 O 3 used as tunneling layer and blocking layer, can reduce leakage current [16], provide lower tunnel barriers, smaller equivalent oxide thicknesses [17], and lower write/erase voltage [18].…”

Evolution of SiO2/Ge/HfO2(Ge) multilayer structure during high temperature annealing

“…HfO 2 is a candidate material for possible replacement of SiO 2 due to its achievable lower equivalent oxide thickness (EOT) which is the layer thickness corresponding to the same capacitance value with a thinner SiO 2 dielectric layer thickness. With a high-k dielectric constant, HfO 2 can be growth thicker to obtain capacitance values equivalent to those obtained with low dielectric materials such as SiO 2 . This results in less leakage current and degradation effects in devices like flash memory cells.…”

“…Thanks to the Fowler-Nordheim tunneling, HfO 2 also provides larger current for charging operation in these devices. Thus, HfO 2 is foreseen as a candidate dielectric material to improve the device performance in memory applications [1][2][3]. In addition, polysilicon floating gates are traditionally used in today's memory elements.…”

Electrical characteristics of MIS capacitors with multi-stack thermal-agglomerating Ge nanocrystals in SiO2/SiNx dielectrics

“…Si NCs/silicon nitride (SiN) and Au NCs/SiN heterogeneous stacks in metal-nitride-oxide-silicon (MNOS) structure have been proposed by Yamazaki et al [10] and Lee et al [11], respectively. Besides, it has been reported that Ge would diffuse into Si substrate during thermal oxidation of SiGe films and thermal-annealing of oxide/Ge/oxide multilayers [8,12]. Ng et al reported the use of SiN/HfO 2 stack as a tunnel dielectric to suppress the Ge penetration during subsequent annealing process to form Ge NCs [12].…”

“…Besides, it has been reported that Ge would diffuse into Si substrate during thermal oxidation of SiGe films and thermal-annealing of oxide/Ge/oxide multilayers [8,12]. Ng et al reported the use of SiN/HfO 2 stack as a tunnel dielectric to suppress the Ge penetration during subsequent annealing process to form Ge NCs [12]. Tzeng employed the tetraethylorthosilicate (TEOS) oxide barriers to suppress Ge diffusion in amorphous Si (a-Si)/polycrystalline SiGe (poly-SiGe)/a-Si oxidation process to form multi-stack Ge NCs [13].…”