Minimization of memory and network contention for accessing arbitrary data patterns in SIMD systems

Al-Mouhamed, Mayez; Seiden, Steven S.

doi:10.1109/12.506432

Cited by 9 publications

(11 citation statements)

References 14 publications

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“…The above results can be generalized [2] to other multistage networks such as Baseline, Cube, Delta, etc. The reason is that for each of these networks the position of a message at the output of some stage admits a formulation that is similar to Equation 3 which gives similar results to Equations 5, 6, and 7.…”

Section: Analysis Of Parallel Memory Organizationmentioning

confidence: 99%

“…Depending on the location of SNS sub-matrices within M , there exist specific SNS matrices [2] for each type of single path network for which the above necessary and sufficient condition is satisfied. Therefore, the above results are true for an arbitrary single path multistage network.…”

Section: Analysis Of Parallel Memory Organizationmentioning

confidence: 99%

“…Therefore, the above results are true for an arbitrary single path multistage network. Moreover, the set of all CPs (d = M s ⊕ x) associated with all SNS matrices M and all values of x are distinct [2]. The number of permutationsd = M s ⊕ x that an arbitrary n-stage multistage network can perform is T n = 2 n 2 , where M is an n × n SNS matrix and x is an n × 1 arbitrary vector (see the appendix for a proof).…”

Section: Analysis Of Parallel Memory Organizationmentioning

confidence: 99%

“…Consider 8 parallel memories and an access pattern of 8 array elements defined by 2 r = 2 rows each has 2 c = 4 columns with strides of 2 r s = 1 and 2 c s = 2 along the row and column, respectively. The first instance of this pattern is the set {(0, 0) + (k r × 2 0 , k c × 2 1 ) : 0 ≤ k r ≤ 1, 0 ≤ k r ≤ 3} = ((0, 0), (0, 2), (0, 4), (0, 6), (1, 0), (1,2), (1,4), (1,6)). Different instances of the same pattern can be defined as We may define other relevant data patterns for the same array.…”

Section: Parallel Memory Access -Backgroundmentioning

confidence: 99%

“…The location of sub-matrices M [i], within M , can be different for each type of network [2]. For an Omega network, sub-matrices…”

Section: Analysis Of Parallel Memory Organizationmentioning

confidence: 99%

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Array Organization in Parallel Memories

Al-Mouhamed

2004

International Journal of Parallel Programming

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The bandwidth mismatch between processor and main memory is one major limiting problem. Although streamed computations have predictable access patterns their references have little temporal locality and are generally too long to cache. A memory and compiler co-optimization aimed at reducing low-level memory accesses using software and hardware locality optimizations is presented. We propose a scalable and predictable parallel memory based on a compiler synthesis of storage schemes for multi-dimensional arrays that are accessed by an arbitrary but known set of data access patterns. Using algebra of non-singular Boolean matrices, we present analysis of conflict-free access to (1) parallel memories, and (2) alignment networks. Finding a multi-pattern storage scheme is one NP-complete problem. An effective compiler heuristic is proposed for finding a the storage matrix that minimizes overall memory access time. This applies to arbitrary linear patterns and arbitrary alignment networks. It is shown that the proposed storage scheme finds an optimal storage scheme for parallel (1) FFT, and (2) bitonic sorting. The proposed storage scheme outperforms statically optimized storages in the case of power-of-2 multi-stride access. The case of non power-of-2 strides is also addressed. The performance and scalability of the proposed parallel memory and its predictable access time are presented using numerical and multimedia algorithms. It is shown that a memory utilization above 83% is achieved by our storage scheme for 64 memories which largely outperforms previous proposals. Our approach provides a tool for matching the storage pattern with the data access patterns needed for embedded systems running streamed computations with predictable data access patterns.

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Section: Analysis Of Parallel Memory Organizationmentioning

confidence: 99%

Section: Analysis Of Parallel Memory Organizationmentioning

confidence: 99%

Section: Analysis Of Parallel Memory Organizationmentioning

confidence: 99%