Minimizing Excess Timing Guard Banding Under Transistor Self-Heating Through Biasing at Zero-Temperature Coefficient

Abstract

Self-Heating Effects (SHE) is known as one of the key reliability challenges in FinFET and beyond. Large timing guardbands are necessary, which we try to reduce. In this work, we propose operating (biasing) processors at Zero-Temperature Coefficient (ZTC) to contain (mitigate) SHE-induced delay. Operating at ZTC allows near-zero timing guard band to protect circuits against SHE. However, a trade-off is found between thermal timing guardband and performance loss from lowering the voltage.

Theoretical Modeling of a Temperature-Dependent Threshold-Voltage Shift in Self-Aligned Coplanar IZTO Thin-Film Transistors

“…In MOSFETs and FinFETs, the silicon substrate itself acts as an effective heat sink, mitigating Joule heating issues. In contrast, SOI-FETs and GAA-FETs are separated from the silicon substrate by an insulator with low thermal conductivity, obstructing the efficient dissipation of the heat generated in the device via the gate insulator. − Unfortunately, the thin-film transistors (TFTs) used by display manufacturers have a similar structure to SOI-FETs, and TFTs are fabricated on glass substrates with poor thermal conductivity. − To date, this self-heating effect has not been intensively investigated in TFT structures because of the relatively low on-current ( I ON ) requirement of display devices.…”