DOI: 10.22215/etd/2016-11240
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Minimizing nMOS Edge Leakage in Fully Depleted Silicon-on-Insulator CMOS Using Poly-Buffered LOCOS Isolation

Abstract: A process has been designed, implemented and tested to minimize edge-leakage effects in fully depleted silicon-on-insulator (FD SOI) nMOSFET (nMOS) devices encountered in previous student project SOI CMOS fabrication runs in the Carleton University Microfabrication Laboratory. A layout with test arrays, including enclosed geometry transistors, was designed to perform a test fabrication run. The process uses optimized oxidation steps and Poly-Buffered LOCal Oxidation of Silicon (PBL) isolation with minimal mask… Show more

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