Minority-carrier injection into polysilicon emitters

Eltoukhy, A.A.; Roulston, D.J.

doi:10.1109/t-ed.1982.20814

Cited by 32 publications

(6 citation statements)

References 12 publications

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“…Our TEM examinations of silicon specimens given nominally the same HF treatment, and sub~equently processed, by different organizations have shown dlfferences in the behavior of the oxide layer which we attribute to differences in its initial thickness. 19 Furthermore, measurements by different organizations of the thickness of oxide layers present on silicon slices after HF treatments have given markedly different values, e.g., [8][9] A from ellipsometryl7 and -3 A from Auger spectroscopy. IS The above TEM results show that the interfacial oxide layers break up faster when they are heated at higher temperatures, and when they are initially thinner.…”

Section: Tem Resultsmentioning

confidence: 99%

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An investigation of the thermal stability of the interfacial oxide in polycrystalline silicon emitter bipolar transistors by comparing device results with high-resolution electron microscopy observations

Wolstenholme

Jorgensen

Ashburn

et al. 1987

Journal of Applied Physics

176

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A comparison is made between the results of high-resolution electron microscope observations and the electrical characteristics of polycrystalline silicon emitter bipolar transistors. Devices are fabricated with and without a deliberately grown interfacial oxide layer, and the thermal stability of this oxide layer is investigated by carrying out a preanneal at temperatures between 800 and 1100 °C after polysilicon deposition, but prior to emitter implant and 900 °C drive-in. The electron microscope observations show that the deliberately grown interfacial oxide is of uniform thickness ∼14 Å, but breaks up when annealed at ∼950 °C and above, with ‘‘balling-up’’ occurring at ∼1100 °C. This correlates with a transistor gain that decreases from ∼1400 to ∼40. The electron microscopy also shows that a thin interfacial oxide layer is present even when not deliberately grown. This oxide breaks up when annealed at ∼900 °C and above, with ‘‘balling-up’’ occurring at ∼1000 °C. This correlates with a transistor gain that decreases from ∼240 to ∼50. Calculations of the effect that such interfacial oxide layers will have on the characteristics of polysilicon emitter bipolar transistors are made, and these predictions correlate well with the measured characteristics.

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Section: Tem Resultsmentioning

confidence: 99%

“…4 • 6 ,7 In this case the gain improvement can be attributed to tunneling through this oxide layer. 8 Eltoukhy and RouIston,9.10 and later Yu et al,11 have published unified theories that incorporate both these mechanisms, the former giving a solution suitable for numerical implementation, the latter a versatile analytical solution.…”

Section: I Introductionmentioning

confidence: 99%

An investigation of the thermal stability of the interfacial oxide in polycrystalline silicon emitter bipolar transistors by comparing device results with high-resolution electron microscopy observations

Wolstenholme

Jorgensen

Ashburn

et al. 1987

Journal of Applied Physics

176

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“…Several theoretical models have been proposed in the literature to account for the current gain increase in polysilicon emitter bipolar transistors. Among these, there are three basic models, the potential barrier model due to the doping atoms segregation at the polysilicon/silicon interface [5,6], the mobility reduction model at the grain boundaries in the polysilicon and at the pseudo-grain boundary at the polysilicon/silicon interface [2,7,8], and finally, the oxide tunnelling model, which explains the improved gain by tunnelling through a thin oxide layer at the polysilicon/silicon interface [1,9]. The choice of one of these models is conditioned by the technology available; we have chosen the tunnel model.…”

Section: Introductionmentioning

confidence: 99%

Minority carrier transport equation for bipolar transistors with polysilicon emitter contact

Zouari¹,

Arab²

2003

phys. stat. sol. (a)

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In order to improve the current gain via a reduction of the emitter base junction saturation current density, a perpendicular ordering of the grain boundaries (columnar grain boundaries) in the polysilicon emitterregion of a bipolar transistor is proposed. The complex polysilicon current component is obtained by a two-dimensional resolution of the current transport equation along the polysilicon region. The minority carrier current density component in the non-uniformly heavily doped single-crystal emitter is calculated by an average value approach. The influence of the two-dimensional structure of the polysilicon region on the current gain is analysed, and it is shown that the current gain decreases with increasing grain number. The evolution of the normalised current gain in terms of physical parameters is studied. The results show that the current gain improves with polysilicon thickness for a thin oxide layer, while it is insensitive for a thick oxide layer. In addition, the results show that the bulk recombination in a single-crystal emitter cannot be neglected in devices with a deliberately grown interfacial oxide. Base c c b p (0) J J G J J .

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“…Ning and Isaac 1980. Fossum and Shibib 1980, Eltoukhy and Roulston 1982. The increase in current gain is due to the decrease in the effective surface recombination velocity S,, at the mono-polysilicon interface and the decrease in the emitter dark saturation current.…”

Section: Introductionmentioning

confidence: 99%

Characteristics of silicon solar cells with polysilicon on the front surface

Mehta¹

1986

Semicond. Sci. Technol.

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This paper presents an analysis of the emitter dark saturation current, the increase in t h e open-circuit voltage V,, and the increase in conversion efficiency q of a silicon solar cell with polysilicon on the front surface. It is shown that for a solar cell with low resistivity (G0.l 52 cm) and a shallow junction (junction depth 60.1 pm) the increase in V,, is 245 mV and the increases in AM0 and AM1 efficiencies are at least 1 % and 1.35%. respectively.

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Minority-carrier injection into polysilicon emitters

Cited by 32 publications

References 12 publications

An investigation of the thermal stability of the interfacial oxide in polycrystalline silicon emitter bipolar transistors by comparing device results with high-resolution electron microscopy observations

An investigation of the thermal stability of the interfacial oxide in polycrystalline silicon emitter bipolar transistors by comparing device results with high-resolution electron microscopy observations

Minority carrier transport equation for bipolar transistors with polysilicon emitter contact

Characteristics of silicon solar cells with polysilicon on the front surface

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