2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2021
DOI: 10.1109/dft52944.2021.9568294
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Mitigation of the impact of across chip systematic process variation using a novel system level design

Nabanita Ghoshal1,
Sree Rama Kc Saraswatula2,
Santosh Yachareni3
et al.
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