2009
DOI: 10.1049/el.2009.3525
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Mixed analogue/digital phase picking algorithm in oversampling burst-mode clock phase alignment

Abstract: A novel mixed analogue/digital design of a phase picking algorithm in an oversampling clock phase recovery is presented. The proposed approach results in reduced processing time, improved integrability with analogue front-end and low noise generation. Simulations of a 10 Gbit/s burst-mode clock phase alignment circuit in a 0.25 mm SiGe BiCMOS process, show a simulated processing delay of only 280 ps.

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Cited by 5 publications
(3 citation statements)
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“…There are mainly three BM-CDR design techniques to tackle this problem as depicted in Fig. 15 [55]: a) a fast-lock phase locked loop (PLL) based CDR [56] and [57], b) a gated-voltage controlled oscillator (G-VCO) based CDR [58]- [61], and c) an over-sampling CDR [62]- [69].…”
Section: Gb/s Bm-cdr Design Architecturesmentioning
confidence: 99%
See 1 more Smart Citation
“…There are mainly three BM-CDR design techniques to tackle this problem as depicted in Fig. 15 [55]: a) a fast-lock phase locked loop (PLL) based CDR [56] and [57], b) a gated-voltage controlled oscillator (G-VCO) based CDR [58]- [61], and c) an over-sampling CDR [62]- [69].…”
Section: Gb/s Bm-cdr Design Architecturesmentioning
confidence: 99%
“…Then the samples are de-serialized in 4 groups of 16 samples. This reduces the speed requirement and provides averaging for the phase picking algorithm [69].…”
Section: Gb/s Over-sampling Bm-cdrsmentioning
confidence: 99%
“…A BM post-amplifier (BM-PA) with automatic reset generation and automatic burst detection was designed for a guard time as short as 25.6 ns and a preamble of ,23.8 ns [4]. A BM clock and data recovery chip (BM-CDR) performs oversampling clock phase recovery using novel mixed analogue/digital phase picking circuitry [5]. The DC-coupled BM receiver (BM-Rx) prototype containing the BM-TIA and the BM-PA ICs was originally designed and characterised for 10 Gbit/s.…”
mentioning
confidence: 99%