Mixed CT/DT Cascaded Sigma-Delta Modulator

Lee, Kye-Shin

doi:10.5573/jsts.2009.9.4.233

Cited by 7 publications

(1 citation statement)

References 19 publications

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“…To solve these problems, many papers suggest different approaches of DSM architecture: The architecture with a feedforward ELD compensation path by residual signal can allow the specification of the feedback DAC to be relaxed [10]. A mixed CT/DT 2-1 cascaded DSM architecture is proposed to achieve both high-speed operation and stability [11]. A DSM with a semi-digital FIR filter in the feedback DAC is proposed to overcome the linearity of the feedback DAC [12].…”

Section: Behavioral Modelingmentioning

confidence: 99%

Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

Na¹,

Kim²,

Yang³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuitlevel simulation using Verilog-A blocks are used to validate our approach.

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Section: Behavioral Modelingmentioning

confidence: 99%

Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

Na¹,

Kim²,

Yang³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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A low-power parametric integrator for wideband switched-capacitor ΣΔ modulators

Seyedhosseinzadeh

Nabavi

2013

Analog Integr Circ Sig Process

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Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System

Park¹,

Sunwoo

Kim³

et al. 2009

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents an efficient synchronizer architecture using a common autocorrelator for Digital Video Broadcasting via Satellite, Second generation (DVB-S2). To achieve the required performance under the worst channel condition and to implement the efficient H/W resource utilization of functional synchronization blocks, we propose a new efficient common autocorrelator structure. The proposed architecture can decrease about 92% of multipliers and 81% of adders compared with the direct implementation. Moreover, the proposed architecture has been thoroughly verified in XilinxTM Virtex IV and R&STM SFU (Signaling and Formatting Unit) broad-cast test equipment.

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Mixed CT/DT Cascaded Sigma-Delta Modulator

Cited by 7 publications

References 19 publications

Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

A low-power parametric integrator for wideband switched-capacitor ΣΔ modulators

Low Complexity Synchronizer Using Common Autocorrelator for DVB-S2 System

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