Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications

Changela, Ankur; Zaveri, Mazad; Verma, Deepak

doi:10.1016/j.vlsi.2021.01.005

Cited by 11 publications

(7 citation statements)

References 22 publications

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“…Parallel pipelined FFT requires less electricity due to lower frequency. FFT uses improved Coordinate Rotation Digital Computer (CORDIC) to build FPGA [24,25]. The expanded optimum CORDIC technique demands a lot of math in the initial step.…”

Section: Proposed Reconfigurable Fftmentioning

confidence: 99%

Reconfigurable Logic Design of CORDIC Based FFT Architecture for 5G Communications

Thiruvengadam¹,

Palanivelan²

2023

Intelligent Automation &Amp; Soft Computing

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There are numerous goals in next-generation cellular networks (5G), which is expected to be available soon. They want to increase data rates, reduce end-to-end latencies, and improve end-user service quality. Modern networks need to change because there has been a significant rise in the number of base stations required to meet these needs and put the operators' low-cost constraints to the test. Because it can withstand interference from other wireless networks, and Adaptive Complex Multicarrier Modulation (ACMM) system is being looked at as a possible choice for the 5th Generation (5G) of wireless networks. Many arithmetic units need to be used on the hardware side of multicarrier systems to do the pulse-shaping filters and inverse FFT. The main goal of this study is to adapt complex multicarrier modulation (ACMM) for baseband transmission with low complexity and the ability to change it. We found that this is the first reconfigurable architecture that lets you choose how many subcarriers a subband has while still having the same amount of hardware resources as before. Also, under the new design with a single selection line, it selects from a set of filters. The baseband modulating signal is evaluated and tested using a Field-Programmable Gate Array (FPGA) device. This device is available from a commercial source. New technology outperforms current technology in terms of computational complexity, simple design, and ease of implementation. Additionally, it has a higher power spectrum density, spectral efficiency, a lower bit error rate, and a higher peak to average power ratio than existing technology.

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Section: Proposed Reconfigurable Fftmentioning

confidence: 99%

Reconfigurable Logic Design of CORDIC Based FFT Architecture for 5G Communications

Thiruvengadam¹,

Palanivelan²

2023

Intelligent Automation &Amp; Soft Computing

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“…Therefore, implementing the modified R4-HV CORDIC algorithm requires adders and 3-to-1 multiplexers, which is significantly less than the 3N adders required by the radix-2 CORDIC algorithm. The proposed R4-HV CORDIC algorithm has better hardware utilization than the radix-2 CORDIC algorithm since the complexity of an adder is approximately twice that of a 3-to-2 multiplexer 30 . In the post-processing stage, the output of the Z -datapath of the last stage of the radix-4 HVCORDIC is shifted right by 1-bit to generate .…”

Section: Modified Radix-4 Cordicmentioning

confidence: 99%

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Changela,

Kumar,

Woźniak

et al. 2023

Sci Rep

Self Cite

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In this article, a low-complexity VLSI architecture based on a radix-4 hyperbolic COordinate Rotion DIgital Computer (CORDIC) is proposed to compute the $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power of a fixed-point number. The most recent techniques use the radix-2 CORDIC algorithm to compute the root and power. The high computation latency of radix-2 CORDIC is the primary concern for the designers. $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power computations are divided into three phases, and each phase is performed by a different class of the proposed modified radix-4 CORDIC algorithms in the proposed architecture. Although radix-4 CORDIC can converge faster with fewer recurrences, it demands more hardware resources and computational steps due to its intricate angle selection logic and variable scale factor. We have employed the modified radix-4 hyperbolic vectoring (R4HV) CORDIC to compute logarithms, radix-4 linear vectoring (R4LV) to perform division, and the modified scaling-free radix-4 hyperbolic rotation (R4HR) CORDIC to compute exponential. The criteria to select the amount of rotation in R4HV CORDIC is complicated and depends on the coordinates $$X^j$$ X j and $$Y^j$$ Y j of the rotating vector. In the proposed modified R4HV CORDIC, we have derived the simple selection criteria based on the fact that the inputs to R4HV CORDIC are related. The proposed criteria only depend on the coordinate $$Y^j$$ Y j that reduces the hardware complexity of the R4HV CORDIC. The R4HR CORDIC shows the complex scale factor, and compensation of such scale factor necessitates the complex hardware. The complexity of R4HR CORDIC is reduced by pre-computing the scale factor for initial iterations and by employing scaling-free rotations for later iterations. Quantitative hardware analysis suggests better hardware utilization than the recent approaches. The proposed architecture is implemented on a Virtex-6 FPGA, and FPGA implementation demonstrates $$19\%$$ 19 % less hardware utilization with better error performance than the approach with the radix-2 CORDIC algorithm.

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“…Later, a hybrid radix 2–4 CORDIC algorithm with high-performance compensation technique waspresented [ 25 ] with reduced number of iterations by 1/4, including scale factor calculation and compensation. Nevertheless, the computation and correction of variable scale factor was a focused issue for higher radix CORDIC algorithms [ 26 , 27 , 28 , 29 ] and advanced hybrid CORDIC algorithms [ 30 ]. The scale-free CORDIC algorithm [ 31 , 32 ] approximated the sine and cosine functions by the Taylor series, thereby eliminating the need for the scalar factors, except for a limited convergence range and poor accuracy.…”

Section: Related Workmentioning

confidence: 99%

A Low-Latency RDP-CORDIC Algorithm for Real-Time Signal Processing of Edge Computing Devices in Smart Grid Cyber-Physical Systems

Qin

Liu

Hou

et al. 2022

Sensors

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Smart grids are being expanded in scale with the increasing complexity of the equipment. Edge computing is gradually replacing conventional cloud computing due to its low latency, low power consumption, and high reliability. The CORDIC algorithm has the characteristics of high-speed real-time processing and is very suitable for hardware accelerators in edge computing devices. The iterative calculation method of the CORDIC algorithm yet leads to problems such as complex structure and high consumption of hardware resource. In this paper, we propose an RDP-CORDIC algorithm which pre-computes all micro-rotation directions and transforms the conventional single-stage iterative structure into a three-stage and multi-stage combined iterative structure, thereby enabling it to solve the problems of the conventional CORDIC algorithm with many iterations and high consumption. An accuracy compensation algorithm for the direction prediction constant is also proposed to solve the problem of high ROM consumption in the high precision implementation of the RDP-CORDIC algorithm. The experimental results showed that the RDP-CORDIC algorithm had faster computation speed and lower resource consumption with higher guaranteed accuracy than other CORDIC algorithms. Therefore, the RDP-CORDIC algorithm proposed in this paper may effectively increase computation performance while reducing the power and resource consumption of edge computing devices in smart grid systems.

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Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications

Cited by 11 publications

References 22 publications

Reconfigurable Logic Design of CORDIC Based FFT Architecture for 5G Communications

Reconfigurable Logic Design of CORDIC Based FFT Architecture for 5G Communications

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

A Low-Latency RDP-CORDIC Algorithm for Real-Time Signal Processing of Edge Computing Devices in Smart Grid Cyber-Physical Systems

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