Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Kamal, Kamal Y.; Mureşan, Radu

doi:10.1109/access.2019.2938729

Cited by 4 publications

(2 citation statements)

References 72 publications

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“…values [107,126,127,67,32,382,359,319] and voltage reduction induced failures [19]; butterfly PUFs, which mimic the behavior of SRAM cells with cross-coupled data latches [179]; latch PUFs, which cross-couple two NOR-gates [309]; flip-flop PUFs, which exploit the power up behavior of regular flip-flops [221,338]; and PUFs for emerging memory technologies [136,177,277,342,59,60,208,71,374,375,343,31,254,149]. These prior works either require additional customized hardware or usage of SRAM, which has a small address space compared to DRAM, and thus cannot accommodate a large number of challenge-response pairs.…”

Section: Memory-based Pufs Include Sram Pufs Which Rely On Sram Start Upmentioning

confidence: 99%

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

Kim

2021

Preprint

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Characterization of real DRAM devices has enabled findings in DRAM device properties, which has led to proposals that significantly improve overall system performance by reducing DRAM access latency and power consumption. In addition to improving system performance, a deeper understanding of DRAM technology via characterization can also improve device reliability and security. These can be seen with the recent discoveries of 1) DRAM-based true random number generators (TRNGs), a method for generating true random numbers using DRAM devices which can be used in many applications, 2) DRAM-based physical unclonable functions (PUFs), a method for generating unique device-dependent keys for identification and authentication, and 3) the RowHammer vulnerability, a phenomenon where repeatedly accessing a DRAM row can cause failures in unaccessed neighboring DRAM rows.To advance DRAM-based discoveries and mechanisms, this dissertation rigorously characterizes many modern commodity DRAM devices and shows that by exploiting DRAM access timing margins within manufacturer-recommended DRAM timing specifications, we can significantly improve system performance, reduce power consumption, and improve device reliability and security. First, we characterize DRAM timing parameter margins and find that certain regions of DRAM can be accessed faster than other regions due to DRAM cell process manufacturing variation. We exploit this by enabling variable access times depending on the DRAM cells being accessed, which not only improves overall system performance, but also decreases power consumption. Second, we find that we can uniquely identify DRAM devices by the locations of failures that result when we access DRAM with timing parameters reduced below specification values. Because we induce these failures with DRAM accesses, we can generate these unique identifiers significantly more quickly than prior work. Third, we propose a random number generator that is based on our observation that timing failures in certain DRAM cells are randomly induced and can thus be repeatedly polled to very quickly generate true random values. Finally, we characterize the RowHammer security vulnerability on a wide range of modern DRAM chips while violating the DRAM refresh requirement in order to directly characterize the underlying DRAM technology without the interference of refresh commands. We demonstrate with our characterization of real chips, that existing RowHammer mitigation mechanisms either are not scalable or suffer from prohibitively large performance overheads in projected future devices and it is critical to research more effective solutions to RowHammer. Overall, our studies build a new understanding of modern DRAM devices to improve computing system performance, reliability and security all at the same time. I have many people to thank for their support during my PhD journey. First and foremost, I am extremely grateful to my advisor, Onur Mutlu, who has generously mentored and guided me since my sophomore year of college. His passion for C...

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Section: Memory-based Pufs Include Sram Pufs Which Rely On Sram Start Upmentioning

confidence: 99%

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

Kim

2021

Preprint

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“…It extends the hardware efficiency by processing multiple values per one operation. The capacitive PUF (CPUF) is proposed by Kamal et al in [30]. The CPUF uses one frequency oscillator to drive eight frequency dividers, with each driver connected to a counter.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET

et al. 2021

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The main purpose of this paper is to achieve ultra-low power Physical Unclonable Function (PUF) to meet the requirements for Internet of Things (IoT) applications. PUFs are promising hardware security primitives that are based on the uniqueness and the unclonability of the device's physical characteristics to provide a unique identifier for devices. PUFs can be used in device authentication and for secure key storage and generation. This paper presents Oscillator Collapse Physical Unclonable Function (OC-PUF), which is suitable for low power applications. The power consumption is reduced based on designing the most power-hungry modules in the OC-PUF. An Oscillator Collapse (OC) is designed to work in the near-threshold voltage region, which reduces the power consumption. More power reduction is achieved by designing a new Collapse Time Comparator (CTC). Due to the process variations, the oscillations period of each OC is different. The CTC generates the output response bit by comparing the oscillations periods of the two selected OCs. The simulation results demonstrate that the proposed OC-PUF can effectively reduce the power consumption. The proposed PUF is designed using 20 nm triple gate FinFET technology. The Simulation results for 1000 different chips with the same input challenge, show that the average power is 140 nW, with the worst case being 740 nW. The best case is 63 nW per challenge-response pair at supply voltage 0.5 V. The averaged reliability of the OC-PUF is 99.8%, at temperatures from-40 to 125 • C and supply voltage 0.5 ± 10%. The proposed OC-PUF decreases the power consumption while retaining high-performance metrics. INDEX TERMS Authentication, hardware security, low power consumption, process variation, reliability, transient effect of ring oscillator.

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Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

Kim¹

2020

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Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells

Cited by 4 publications

References 72 publications

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

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