Mixed signal SIMD processor array vision chip for real-time image processing

Carey, Stephen J.; Barr, David R. W.; Wang, Bin; Lopich, Alexey; Dudek, Piotr

doi:10.1007/s10470-013-0192-x

Cited by 17 publications

(6 citation statements)

References 30 publications

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“…A peculiarity of this device is the design of its PEs featuring a mixed-signal circuitry [2]: each cell includes seven analog registers and thirteen singlebit digital registers. This design allows a reasonable trade-off between the silicon area required to implement the ALU and its registers, its power consumption, and the "computational primitives" it provides.…”

Section: Architecture Of the Scamp-5 Vision-chipmentioning

confidence: 99%

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A Neuromorphic Approach for Tracking using Dynamic Neural Fields on a Programmable Vision-chip

Martel

Sandamirskaya

2016

Proceedings of the 10th International Conference on Distributed Smart Camera

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In artificial vision applications, such as tracking, a large amount of data captured by sensors is transferred to processors to extract information relevant for the task at hand. Smart vision sensors offer a means to reduce the computational burden of visual processing pipelines by placing more processing capabilities next to the sensor. In this work, we use a vision-chip in which a small processor with memory is located next to each photosensitive element. The architecture of this device is optimized to perform local operations. To perform a task like tracking, we implement a neuromorphic approach using a Dynamic Neural Field, which allows to segregate, memorize, and track objects. Our system, consisting of the vision-chip running the DNF, outputs only the activity that corresponds to the tracked objects. These outputs reduce the bandwidth needed to transfer information as well as further post-processing, since computation happens at the pixel level. ABSTRACTIn artificial vision applications, such as tracking, a large amount of data captured by sensors is transferred to processors to extract information relevant for the task at hand. Smart vision sensors offer a means to reduce the computational burden of visual processing pipelines by placing more processing capabilities next to the sensor. In this work, we use a vision-chip in which a small processor with memory is located next to each photosensitive element. The architecture of this device is optimized to perform local operations.To perform a task like tracking, we implement a neuromorphic approach using a Dynamic Neural Field, which allows to segregate, memorize, and track objects. Our system, consisting of the vision-chip running the DNF, outputs only the activity that corresponds to the tracked objects. These outputs reduce the bandwidth needed to transfer information as well as further post-processing, since computation happens at the pixel level.

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Section: Architecture Of the Scamp-5 Vision-chipmentioning

confidence: 99%

“…In this work we propose an approach using an algorithm running on such a vision-chip that embeds an array of processors [2]. The vision-chip consists of processing elements with memory organized on a grid; each of them is placed next to a photosensitive element.…”

Section: Introductionmentioning

confidence: 99%

A Neuromorphic Approach for Tracking using Dynamic Neural Fields on a Programmable Vision-chip

Martel

Sandamirskaya

2016

Proceedings of the 10th International Conference on Distributed Smart Camera

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“…Obtained values show good performance if compared with Ginhac et al 25 (4% in 20 ms) or with Carey et al 26 (5% in 1 s). However, our results come from electrical simulations whereas Ginhac et al 25 and Carey et al 26 report measurements from fabricated chips. Also, no information is given about how these data were extracted and if the measurement process could affect the results.…”

Section: Drift (Mv/s)mentioning

confidence: 48%

In‐pixel analog memories for a pixel‐based background subtraction algorithm on CMOS vision sensors

Garcia-Lesta

López

Brea

et al. 2018

Circuit Theory & Apps

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This paper addresses the most suitable in-pixel analog memory bank for running a hardware-oriented approach of the well-known Pixel-Based Adaptive Segmenter algorithm on CMOS vision sensors. The high number of memory accesses, typically up to 200 times, along with the long time elapsed before an analog memory in a pixel is updated, around 5 seconds at 30 fps, constrains the memory topology. This work assesses the impact of nominal and process nonidealities of the 3 main analog memory topologies, namely, open-loop, closed-loop, and integrator architectures for background subtraction over the CDNET14 database. This is the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the Pixel-Based Adaptive Segmenter. KEYWORDS analog memories, background subtraction, CMOS vision sensors, focal plane processing, PBAS *Corrections added on 25 April 2018, after first online publication: several incorrect citations have been corrected and a missing reference [19] has been added.

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“…PPA sensors consist of a parallel array of neighborconnected processing elements, each of which features light capture, processing and storage capabilities allowing for various image processing tasks to be efficiently performed directly on the focal plane itself [4], [15], [9], [1], [2], [19]. This is in contrast to traditional camera sensors in which each pixel element is only capable of light capture, meaning that whole images must be transferred to a separate external device for processing.…”

Section: Introductionmentioning

confidence: 99%