Mixed-signal System-on-a-Chip (SoC) verification based on SystemVerilog model

Yang, Xiaokun; Niu, Xinwei; Fan, Jeffrey; Choi, Chiu

doi:10.1109/ssst.2013.6524952

Cited by 11 publications

(2 citation statements)

References 2 publications

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“…However, their definition is often a complex task. To minimize designers' efforts and potential for human mistakes, multiple works [5]- [7] defined methodologies and parametric models' templates to generate RNMs. Others [8] built a template library of HDL-defined analog components covering different circuits' classes to model complex designs' behavior.…”

Section: State Of the Artmentioning

confidence: 99%

Using High-Level Synthesis to model System Verilog procedural timing controls

Pozzoni,

Ferrandi,

Mendola

et al. 2023

2023 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In modern SoC designs, digital components' development and verification processes often depend on the component's interactions with other digital and analog modules on the same die. While designers can rely on a wide range of tools and practices for validating fully-digital models, porting the same workflow to mixed models' development requires significant efforts from the designers. A common practice is to use Real Number Modeling techniques to generate HDL-based behavioral models of analog components to efficiently simulate mixed models using only eventbased simulations rather than Analog Mixed Signals (AMS) simulations. However, some of these models' language features are not synthesizable with existing synthesis tools, requiring additional efforts from the designers to generate post-tapeout prototypes. This paper presents a methodology for transforming some non-synthesizable SystemVerilog language features related to timing controls into functionally-equivalent synthesizable Verilog constructs. The resulting synthesizable models replicate their respective RNMs' behavior while explicitly managing delay controls and event expressions. The RNMs are first transformed using the MLIR framework and then synthesized with open-source HLS tools to obtain FPGA-synthesizable Verilog models.

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Section: State Of the Artmentioning

confidence: 99%

Using High-Level Synthesis to model System Verilog procedural timing controls

Pozzoni,

Ferrandi,

Mendola

et al. 2023

2023 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

View full text Add to dashboard Cite

show abstract

“…The verification of multiprocessor system-on-chips (MSoC) was discussed [30], a model of MSoC was proposed, in the model, the multiprocessor was modelled by a number of processing elements, an application on the MSoC was modelled by task graph, the verification of MSoC was performed by translated the model to timed automata. The verification of the mixedsignal in a complex SoC was discussed [31], a high-level radio frequency model was built by using SystemVerilog language, the model can be executed on the digital simulators. An approach that can formally prove protocol compliance for the communication blocks in SoC was investigated [32], the approach used both the property checking on a bounded circuit model with the approximate reach-ability analysis.…”

Section: Introductionmentioning

confidence: 99%

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Zhang

Ling²,

Chen³

2014

TOEEJ

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Abstract:The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

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Earth Mover’s Distance as a Comparison Metric for Analog Behavior

Rath

Simon

Esen

et al. 2017

IFIP Advances in Information and Communication Technology

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Evaluating the outcome of analog simulations is a common, mostly manually carried out task in the pre-silicon verication process of mixed-signal ICs. Its non-automated nature makes it an error-prone and time-consuming procedure. For this very reason, we introduce a novel approach for performing this evaluation automatically resulting in signicantly reduced turnaround times as well as a considerably increased reliability of verication results. The presented concept is motivated by an algorithm that is used in optical pattern recognition and is called Earth Mover's Distance. Furthermore, we compare our approach with already existing algorithms, namely Fréchet Distance and Pearson Coecient, in order to analyze its capability. Finally, we present a case study in which we prove the algorithm by applying it to the results of a mixed-signal simulation at chip-level demonstrating the eciency of our approach.

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Mixed-signal System-on-a-Chip (SoC) verification based on SystemVerilog model

Cited by 11 publications

References 2 publications

Using High-Level Synthesis to model System Verilog procedural timing controls

Using High-Level Synthesis to model System Verilog procedural timing controls

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Earth Mover’s Distance as a Comparison Metric for Analog Behavior

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