MMLSTOGI based control for suppression of current harmonics in PV‐tied grid

An active clamped L‐L type ZVS current‐fed front‐end DC–DC converter based solid state transformer in grid connected mode PV applications

“…And, $$$$\begin{equation*}{A_{hn}}{\mathrm{}}\left( s \right) = \frac{{{J_{hn}}\left( s \right)}}{{{K_1}E\left( s \right)}}\end{equation*}$$$$ $$$$\begin{equation} = \frac{{n{K_{1}}{W^2}s}}{{\left( {{s^3} + n{K_{3}}W{s^2} + \left( {1 + \frac{{{K_1}}}{n}} \right){{\left( {nW} \right)}^2}s + {K_{3}}{{\left( {nW} \right)}^3}} \right)}}\end{equation}$$$$where n is the order of the harmonic components at which the DFSEn filter is tuned. Therefore, the final transfer function can be given by [26, 27]: $$$$\begin{equation}{G_{1\alpha }}\left( s \right) = \frac{{{J_\alpha }\left( s \right)}}{{J\left( s \right)}} = {C_1}\left( s \right)\left[ {1 - \mathop \sum \limits_{n = 3,5,7,11} {A_{hn}}\left( s \right)} \right]\end{equation}$$$$…”

“…The VSC utilizes the current controlled mode (CCM) control algorithm [26] to control the power flow to the grid. The complete diagram depicting the control algorithm is provided in Figure 7.…”

“…where n is the order of the harmonic components at which the DFSEn filter is tuned. Therefore, the final transfer function can be given by [26,27]:…”

“…Many topologies such as DFSE [24], cascading of two SOGIs as in‐loop filters or pre‐filters [25], were proposed to mend these deficits, but still problem of lower order harmonics and slow response persisted. In order to mitigate these problems, a new topology based on [19], was presented in [26] as mixed multi‐level second and third order generalized integrator (MMLSTOGI) and was modified as multilayer modified quadrature signal generator (MMQSG) in [27]. The presented work further extends the effectiveness of these topologies by further improving the response speed and precision of the extracted fundamental components and termed as multi‐level cascaded dual double fundamental signal extractor (MCDDFSE).…”

DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applications

“…A mixed second-and third-order generalized integrator (MSTOGI)-based PLL is presented in [16,17]; it contains an extra branch to the SOGI block to eliminate DC offset and high-frequency harmonics from input signals. The MSTOGI gain affects the filtering capability, dynamic performance, and bandwidth of the SRF-PLL.…”