Mobile GPU accelerated digital predistortion on a software-defined mobile transmitter

Li, Kaipeng; Ghazi, Amanullah; Boutellier, Jani; Abdelaziz, Mahmoud; Anttila, Lauri; Juntti, Markku; Valkama, Mikko; Cavallaro, Joseph R.

doi:10.1109/globalsip.2015.7418298

Cited by 6 publications

(5 citation statements)

References 16 publications

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“…Moreover, the LS problem is often poorly conditioned [4]. In [10], a mobile graphics processing units (GPU) was used to implement the polynomial DPD with I/Q imbalance correction from [4]. This GPU implementation used floating-point and was able to avoid the challenges associated with the dynamic range requirements for memory polynomials.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Neural Network Based Predistorter for Enhanced Mobile Broadband

Tarver

Balatsoukas‐Stimming

Cavallaro

2019

2019 IEEE International Workshop on Signal Processing Systems (SiPS)

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Digital predistortion is the process of correcting for nonlinearities in the analog RF front-end of a wireless transmitter. These nonlinearities contribute to adjacent channel leakage, degrade the error vector magnitude of transmitted signals, and often force the transmitter to reduce its transmission power into a more linear but less power-efficient region of the device. Most predistortion techniques are based on polynomial models with an indirect learning architecture which have been shown to be overly sensitive to noise. In this work, we use neural network based predistortion with a novel neural network training method that avoids the indirect learning architecture and that shows significant improvements in both the adjacent channel leakage ratio and error vector magnitude. Moreover, we show that, by using a neural network based predistorter, we are able to achieve a 42% reduction in latency and 9.6% increase in throughput on an FPGA accelerator with 15% fewer multiplications per sample when compared to a similarly performing memory-polynomial implementation.

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Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Neural Network Based Predistorter for Enhanced Mobile Broadband

Tarver

Balatsoukas‐Stimming

Cavallaro

2019

2019 IEEE International Workshop on Signal Processing Systems (SiPS)

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“…One of the examples of such a problem is the delay time due to finite speed of processor calculations and its relation to maximal network latency (which is defined as time it takes data to travel from one point to another) of less than 1 ms in 5G, which we mentioned in the introduction. In [93][94][95], the delay of DPD, depending on the implementation (FPGA, GPU, ASIC), is evaluated to be tens to hundreds of microseconds. Taking into account the fact that signal may have to pass through multiple DPD stages and through the whole data transfer system, it is possible DPD delay will be a major bottleneck in overall system latency.…”

Section: Discussionmentioning

confidence: 99%

Linearization as a Solution for Power Amplifier Imperfections: A Review of Methods

2021

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Development of 5G networks requires a substantial increase to both spectral and power efficiency of transmitters. It is known that these two parameters are subjected to a mutual trade-off. To increase the linearity without losing power efficiency, linearization techniques are applied to power amplifiers. This paper aims to compare most popular linearization techniques to date and evaluate their applicability to upcoming 5G networks. The history of each respective linearization technique is followed by the main principle of operation, revealing advantages and disadvantages supported by concluding the latest research results. Three main groups of linearization methods currently known are feedforward, feedback, and predistortion, each with its own tradeoffs. Although digital predistortion seems to be the go-to method currently, other techniques with less research attention are still non-obsolete. А generalized discussion and a direct comparison of techniques analyzed are presented at the end of this paper. The article offers a systematic view on PA linearization problems which should be useful to researchers of this field. It is concluded that there are still a lot of problems that need to be addressed in every linearization technique in order to achieve 5G specifications.

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“…However, few DPD implementations have been done on such general purpose processors, especially mobile processors considering our DPD design targets mobile transmitters. Our previous work [19], to the best of the authors' knowledge, is the first CUDA-based DPD implementation on GPU, and this paper extends from our previous mobile GPU based DPD implementation with further design optimization and thus higher data rate, and details another embedded CPU-based design for comparison. [20] also proposes an alternative implementation on mobile GPU using OpenCL.…”

Section: Introductionmentioning

confidence: 91%

“…On desktop GPUs which support CUDA, we can invoke even more threads and thread-blocks to realize data parallelism on thousands of CUDA cores, and can perform multi-stream scheduling for pipelining CPU-GPU memory copy and kernel execution as an alternative technique of zero copy to resolve memory copy overhead. Our previous work [19] has discussed DPD performance on desktop GPUs as reference. On desktop CPUs, we can take advantage of even longer SIMD instructions, such as SSE and AVX, with 256-bit or 512-bit registers, and generate more OpenMP threads on more CPU cores for higher performance.…”

Section: Design Summary and Comparisonmentioning

confidence: 99%

“…On the GPU, we implement the computing flow by CUDA kernel functions, and invoke the kernel with large number of parallel threads to perform the computation in parallel based on single instruction multiple threads (SIMT) execution model. In our previous work [19], we have designed three kernels to perform polynomial computation, filtering computation and accumulation, which are invoked with N , N R, N threads, respectively, indicating their parallelism degrees. However, in this way, we need to share intermediate results between those kernels using GPU global memory, which will pose significant memory access overhead.…”

Section: Data Vectorization On Gpumentioning

confidence: 99%

See 1 more Smart Citation

Parallel Digital Predistortion Design on Mobile GPU and Embedded Multicore CPU for Mobile Transmitters

Ghazi

Tarver

et al. 2017

J Sign Process Syst

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Digital predistortion (DPD) is a widely adopted baseband processing technique in current radio transmitters. While DPD can effectively suppress unwanted spurious spectrum emissions stemming from imperfections of analog RF and baseband electronics, it also introduces extra processing complexity and poses challenges on efficient and flexible implementations, especially for mobile cellular transmitters, considering their limited computing power compared to basestations. In this paper, we present high data rate implementations of broadband DPD on modern embedded processors, such as mobile GPU and multicore CPU, by taking advantage of emerging parallel computing techniques for exploiting their computing resources. We further verify the suppression effect of DPD experimentally on real radio hardware platforms. Performance evaluation results of our DPD design demonstrate the high efficacy of modern general purpose mobile processors on accelerating DPD processing for a mobile transmitter.

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Mobile GPU accelerated digital predistortion on a software-defined mobile transmitter

Cited by 6 publications

References 16 publications

Design and Implementation of a Neural Network Based Predistorter for Enhanced Mobile Broadband

Design and Implementation of a Neural Network Based Predistorter for Enhanced Mobile Broadband

Linearization as a Solution for Power Amplifier Imperfections: A Review of Methods

Parallel Digital Predistortion Design on Mobile GPU and Embedded Multicore CPU for Mobile Transmitters

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