Mobility enhancement of strained Si by optimized SiGe/Si/SiGe structures

Huang, S.-H.; Lu, T. M.; Lu, S.-C.; Lee, C.-H.; C, Liu; Tsui, D. C.

doi:10.1063/1.4739513

Appl. Phys. Lett.

2012

DOI: 10.1063/1.4739513

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Mobility enhancement of strained Si by optimized SiGe/Si/SiGe structures

S.-H. Huang

T. M. Lu

S.-C. Lu

et al.

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Cited by 32 publications

(22 citation statements)

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“…4 The development of atomic-layer-deposited (ALD) Al 2 O 3 allowed for the fabrication of undoped heterostructure field-effect transistors (HFET) 6 in which the mobility of Si/SiGe quantum wells was further improved to ∼ 2 × 10 6 cm 2 /(V · s) at 0.3 K and a density of ∼ 1.4 × 10 11 cm −2 . 7 This massive mobility increase opens up the possibility to fabricate and improve upon Si/SiGe nano-devices such as quantum wires 8,9 and quantum dots. [10][11][12][13] When patterning nano-structures, a balance must be attained between high mobility, usually achieved in channels buried deep underneath the surface (∼ 500 nm), and a sharp confinement potential, which is sharper the shallower the channel is.…”

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confidence: 99%

“…6,7 Prior to the growth, the 10 Ω · cm p-type Si (100) substrate was dipped in 10% HF solution and the growth chamber was pre-baked and coated with Si. A graded SiGe virtual substrate was first grown, reaching a 14% Ge composition and ∼ 1.4 µm in thickness.…”

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“…In order to electrically measure the devices, HFETs were fabricated following a process flow similar to previous reports, 6,7 with the notable difference that the Ohmics contacts were defined using ion implantation of phosphorus, followed by an anneal at 625…”

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Scattering mechanisms in shallow undoped Si/SiGe quantum wells

et al. 2015

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We report the magneto-transport study and scattering mechanism analysis of a series of increasingly shallow Si/SiGe quantum wells with depth ranging from ∼ 100 nm to ∼ 10 nm away from the heterostructure surface. The peak mobility increases with depth, suggesting that charge centers near the oxide/semiconductor interface are the dominant scattering source. The power-law exponent of the electron mobility versus density curve, μ ∝ nα, is extracted as a function of the depth of the Si quantum well. At intermediate densities, the power-law dependence is characterized by α ∼ 2.3. At the highest achievable densities in the quantum wells buried at intermediate depth, an exponent α ∼ 5 is observed. We propose and show by simulations that this increase in the mobility dependence on the density can be explained by a non-equilibrium model where trapped electrons smooth out the potential landscape seen by the two-dimensional electron gas.

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Scattering mechanisms in shallow undoped Si/SiGe quantum wells

et al. 2015

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“…The semiconducting properties of Si, Ge, and their alloy SiGe have been well studied in the last forty years. [14][15][16][17][18] Recently, the semiconducting and optoelectronic properties of an alloy, GeSn, have been reported. [19][20][21][22][23][24][25] Group IV-A semiconducting alloys are of interest particularly because their band gap can be adjusted by changing their relative concentration.…”

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SiSn diodes: Theoretical analysis and experimental verification

Hussain

Wehbe

Hussain

2015

Applied Physics Letters

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We report a theoretical analysis and experimental verification of change in band gap of silicon lattice due to the incorporation of tin (Sn). We formed SiSn ultra-thin film on the top surface of a 4 in. silicon wafer using thermal diffusion of Sn. We report a reduction of 0.1 V in the average built-in potential, and a reduction of 0.2 V in the average reverse bias breakdown voltage, as measured across the substrate. These reductions indicate that the band gap of the silicon lattice has been reduced due to the incorporation of Sn, as expected from the theoretical analysis. We report the experimentally calculated band gap of SiSn to be 1.11 ± 0.09 eV. This low-cost, CMOS compatible, and scalable process offers a unique opportunity to tune the band gap of silicon for specific applications.

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“…For example, the lattice mismatch between new channel materials and Si substrates can generate dislocations at the interface, which degrades performance and yield. To mitigate these effects, graded relaxed buffers, 3 dislocation removal, 4 and aspect ratio trapping 5 to reduce the dislocation density in active areas have all been explored. To date, the performance of these hybrid devices has not matched expectations.…”

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New materials for post-Si computing

Östling

Hannon³

2014

MRS Bull.

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Up until the late 1990s, the performance gains implied by "Moore's Law"-the number of transistors on an integrated circuit doubles about every node-in microelectronics were achieved mainly through what is now called traditional scaling. 1Roughly speaking, scaling corresponds to shrinking the device dimensions and supply voltage by a constant factor while leaving the materials unchanged.2 The benefi ts of scaling are increased circuit density, faster devices, and lower power consumption. Note that the performance gains of traditional scaling are not predicated on improvements in materials properties (e.g., channel mobility and gate dielectric permittivity). They are mainly due to reduced capacitance and lower supply voltage. Unfortunately, we are now faced with the reality that fundamental materials limitations make traditional scaling of Si technology problematic. The consensus view is that continued performance improvement requires new materials, new device geometries, and new switching concepts.Replacing Si with high-mobility channel materials (e.g., Ge/GeSn or III-V compounds) ( Figure 1 ) is one near-term approach to improving performance (see the Gupta et al. article in this issue). However, replacing Si and SiO 2 is not a trivial task, and complex "integration" issues must be overcome. For example, the lattice mismatch between new channel materials and Si substrates can generate dislocations at the interface, which degrades performance and yield. To mitigate these effects, graded relaxed buffers, 3 dislocation removal, 4 and aspect ratio trapping 5 to reduce the dislocation density in active areas have all been explored. To date, the performance of these hybrid devices has not matched expectations.For example, while bulk Ge has both high electron and hole mobility ( Figure 1 ), Ge n-channel metal oxide semiconductor fi eld-effect transistors (MOSFETs) do not exhibit the expected mobility enhancement as compared to Si MOSFETs. Currently, III-V (InGaAs) channels are more promising for NFETs. Ge and III-V materials have the appeal that they can be grown on a surface in a similar way as Si, which may make them easier to incorporate in a conventional processing fl ow. A more radical approach is to use novel one-dimensional (1D) (nanotubes, nanowires) or 2D (graphene, dichalcogenides) nanomaterials in place of conventional semiconductors. Because they are "small," these materials offer better electrostatic control of the channel, but their integration with conventional processing is potentially very diffi cult. Finally, devices such as the "tunnel FET" achieve high performance by incorporating new channel materials that enable device switching over a narrow voltage range, and hence with lower power. Moving away from conventional planar devices is another approach to improving performance. Better electrostatic control can be obtained if the gate "wraps around" the channel. New materials for post-Si computing C.W. Liu , M. Östling , and J.B. Hannon , Guest EditorsIt is now widely recognized that continued performa...

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Mobility enhancement of strained Si by optimized SiGe/Si/SiGe structures

Cited by 32 publications

References 16 publications

Scattering mechanisms in shallow undoped Si/SiGe quantum wells

Scattering mechanisms in shallow undoped Si/SiGe quantum wells

SiSn diodes: Theoretical analysis and experimental verification

New materials for post-Si computing

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