Mobility extraction in sub 10nm nanowire nMOSFETs with gadolinium-silicate as gate dielectric

Abstract

Gadolinium-silicate (GdSiO) as high-k dielectric in sub 10nm gate first nanowire (NW) nMOSFETs is investigated. NW-and UTB-nMOSFETs with conventional SiO 2 /Poly-Si gate stacks have been fabricated and compared with GdSiO/TiN NW nMOSFETs. Specific nMOSFETs with multiple NWs in parallel have been used to extract the effective mobility by split-CV method and to eliminate the series resistance to correct the measured data. IntroductionHigh-k dielectric gadolinium silicate (GdSiO) films with large band offsets to silicon, a dielectric constant of 16 provide an attractive scaling potential for future low power applications [1][2][3]. Thermal stability up to 1000°C -a key issue for gate first integration -has been demonstrated for uncapped films in combination with titanium nitride (TiN) electrodes [1][2][4].In addition to an excellent control of V th one dimensional nanostructures are potentially attractive increase of severely depressed SCE and higher I On /I Off ratios [5] [6].A major disadvantage of UTB SOI, FinFETs and NW MOSFETs however, is the concurrent increase of parasitic source to drain resistances, especially if silicon the thickness drops below 10 nm of the silicon film. This inherent feature may eventually be solved by selective epitaxy and/or silicided source drain leads [7][8]. One of the key features, the inversion channel mobility of MOSFETs, can not be extracted from standard split C/V measurements accurately if the high access resistance problem is not addressed appropriately [9].For UTB structures, a special mobility test structure has been proposed and applied to UTB SOI and sSOI devices [9]-[12]. This structure features contacts to the inversion channel to allow four-probe measurements where the series resistance effects can be eliminated. For NW-or FinFETs, however, this structure can not be employed as an inversion layer contact would disrupt the main transistor channel on the Fin/NW sidewall. Instead, we propose to use a different approach with several devices to extract the real series resistance and to correct the measured split C/V data. Experimental Device LayoutKey for the correct mobility (μ eff ) extraction by the split CV technique according to equation 1 is the exact knowledge of the voltage drop V DS inside the channel and the exact measurement of the inversion charge density Q inv . The other parameters in equ. 1 are the gate length L, the gate width W (extracted from TEM images) and the measured drain source current I DS .) (The proposed design for NW MOSFETs feature two "sense" contacts in addition to the conventional source and drain contacts (V L/R , Fig. 1). Furthermore, to address large gate areas and therefore to measure an adequate gate to channel capacitance, very long (L G =100μm) and multiple NWs in parallel are fabricated for split CV method. Fig. 1: Optical micrograph (top view) of a SOI NW nMOSFET with 400 NWs in parallel and additional contacts close to the channel (V L/R ). Q inv can be determined directly by integrating the gate channel capacitance C gc mea...

(Invited) TmSiO as a CMOS-Compatible High-k Dielectric

“…Whereas promising results have been shown for deposited oxides such as SrO and BeO (20,21), achieving controlled and reproducible thickness in the sub-nm regime (which is necessary given the relatively low dielectric constant of the dielectrics most suitable for integration as IL) is extremely challenging for any deposition method. The formation of a silicate IL by thermal reaction is especially interesting in this respect, since it can potentially provide excellent thickness control in the sub-nm regime and since many silicates (especially those formed from lanthanide oxides) have been reported to achieve excellent interface quality with Si (22)(23)(24)(25)(26).…”